1fc79592b7
gallium/tgsi: Remove support for f64 src modifiers.
...
The tgsi.rst was not very clear but didn't indicate that they were
supported, and llvmpipe only supported double abs and not negate.
glsl_to_tgsi never generated them, and neither did the new nir_to_tgsi, so
just garbage collect it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Reviewed-by: Gert Wollny <gert.wollny@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369 >
2021-01-13 22:52:10 +00:00
9a2cbe02ed
gallium/tgsi: Assert that we don't see integer abs modifiers.
...
tgsi.rst says it's not supported, and llvmpipe, r600, and virgl don't
support it. Make sure nobody else introduces them like I did while
testing only on softpipe.
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Reviewed-by: Gert Wollny <gert.wollny@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369 >
2021-01-13 22:52:10 +00:00
1ff2c01741
gallium/ntt: Stop lowering integer source mods.
...
While tgsi_exec.c (softpipe) implemented 32b integer src mods, the
tgsi.rst documentation says only 32b negate is supported and not abs.
llvmpipe implemented 32 and 64 negate but not abs, virgl implemented
negate incorrectly, and r600 apparently doesn't do any integer src mods.
glsl_to_tgsi has apparently never generated integer src mods.
Given that r600 can't do any integer src mods, just stop trying to
generate them for TGSI.
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Reviewed-by: Gert Wollny <gert.wollny@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369 >
2021-01-13 22:52:10 +00:00
ecaa7c3e39
gallium/ttn: Add support for TGSI_OPCODE_I64NEG/ABS.
...
Found when converting AMD's built-in TGSI shaders to not using 64-bit src
mods.
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369 >
2021-01-13 22:52:10 +00:00
8c7526afd2
nv50,nvc0: explicitly list recently-added caps
...
Some of these should be implemented, but that can be done in a later
change.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu >
Reviewed-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8461 >
2021-01-13 17:19:32 -05:00
be7e12d81b
nv50/ir: ignore FS_BLEND_EQUATION_ADVANCED
...
It's unsupported, but gets set unconditionally by the state tracker,
even when fbfetch is to be used.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu >
Reviewed-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8461 >
2021-01-13 17:19:19 -05:00
9d651d2a0f
zink: clamp sampler+samplerview limits
...
* struct shader_info provides a 32bit mask for textures_used
* samplers and samplerviews are a 1:1 mapping for shader descriptors
* also according to spec this is always 32 per stage
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8457 >
2021-01-13 21:53:56 +00:00
f4902bb189
intel/genxml,anv,iris: Drop the legacy compute path from gen125.xml
...
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:28 -08:00
32857a6350
iris: Add support for COMPUTE_WALKER
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:28 -08:00
8f85e68dea
anv: Enable push constants on gen12-hp
...
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:28 -08:00
369eab9420
intel/fs: Emit code for Gen12-HP indirect compute data
...
Reworks:
* Jordan: Apply to gen > 12
* Jordan: Adjust comment about loading constants
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:28 -08:00
4077ca1cc8
anv: Add a general state pool
...
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:28 -08:00
a6f8d59142
anv: Use COMPUTE_WALKER for gen12-hp
...
Rework: Rafael Antognolli, Jason Ekstrand
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:28 -08:00
91fe96cfbe
anv: Don't use MEDIA_INTERFACE_DESCRIPTOR_LOAD for gen12-hp
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:27 -08:00
435b272241
anv: Emit CFE_STATE for gen12-hp
...
Rework:
* make scratch TODO. (Jason)
* emit_compute_cs_state => emit_compute_state. (Jason)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:27 -08:00
b4ffbf1521
intel/fs: Allow compute dispatch without a pushed subgroup ID on Gen12-HP
...
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:27 -08:00
9294193098
intel/compiler: Disable push constants on gen12-hp
...
We currently don't use push constants with the COMPUTE_WALKER command.
Make all uniforms to be pull constants.
The local group id previously was a push constant, but is now
available in R0.2[7:0].
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:27 -08:00
b7c1ad00fc
intel/tools: Decode COMPUTE_WALKER
...
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:27 -08:00
cdc9e22a3a
intel/genxml/gen125: Add CFE_STATE and COMPUTE_WALKER
...
Reworks:
* Jason: Captalize COMPUTE_WALKER::BTD mode
* Jason: Make COMPUTE_WALKER::InlineData an array
* Jason: Remove stale fields, uint=>bool, add missing enum values.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342 >
2021-01-13 13:10:27 -08:00
9149d71bb6
docs: update calendar for 21.0.0-rc1
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478 >
2021-01-13 20:25:25 +00:00
68b1e7b234
docs: update calendar and link releases notes for 20.3.3
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478 >
2021-01-13 20:25:25 +00:00
60ffde5994
docs: Add sha256sum for 20.3.3
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478 >
2021-01-13 20:25:25 +00:00
1a20041361
docs: add release notes for 20.3.3
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478 >
2021-01-13 20:25:25 +00:00
86101cdad7
panfrost: Don't skip the test with a 4k shader
...
Commit bfcdc8f174boris.brezillon@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8470 >
2021-01-13 19:17:33 +00:00
dfe429eb41
nir/loop_unroll: unroll more aggressively if it can improve load scheduling
...
Significantly improves performance of a Control compute shader. Also seems
to increase FPS at the very start of the game by ~5% (RX 580, 1080p,
medium settings, no MSAA).
fossil-db (Sienna):
Totals from 81 (0.06% of 139391) affected shaders:
SGPRs: 3848 -> 4362 (+13.36%); split: -0.99%, +14.35%
VGPRs: 4132 -> 4648 (+12.49%)
CodeSize: 275532 -> 659188 (+139.24%)
MaxWaves: 986 -> 906 (-8.11%)
Instrs: 54422 -> 126865 (+133.11%)
Cycles: 1057240 -> 750464 (-29.02%); split: -42.61%, +13.60%
VMEM: 26507 -> 61829 (+133.26%); split: +135.56%, -2.30%
SMEM: 4748 -> 5895 (+24.16%); split: +31.47%, -7.31%
VClause: 1933 -> 6802 (+251.89%); split: -0.72%, +252.61%
SClause: 1179 -> 1810 (+53.52%); split: -3.14%, +56.66%
Branches: 1174 -> 1157 (-1.45%); split: -23.94%, +22.49%
PreVGPRs: 3219 -> 3387 (+5.22%); split: -0.96%, +6.18%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6538 >
2021-01-13 18:54:18 +00:00
74748f16c9
freedreno/ir3: Remove legacy packed-struct encoding
...
Note that we can't actually remove the packed structs themselves yet,
because tu still uses them in some hand-coded blit shaders.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:48 +00:00
1a8113fdee
freedreno/ir3/decode: Switch over to new disasm
...
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:48 +00:00
668943e9f7
freedreno/ir3: Realign disasm shader stats
...
To better match up with what mesa shader-db stats look like, for easier
comparision.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
3e15ba5ccc
freedreno/ir3: Better sstall estimation
...
1) Take into account repeat/nop cycles
2) Clear sfu_delay after an (ss) sync
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
11cba228fd
freedreno/ir3: Small resinfo disasm tweak
...
Add the 'type' field.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
5cae4779c2
freedreno/ir3: Switch over to new encoder/decoder
...
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
01e8bd55de
freedreno/ir3/tests: Switch disasm test over to new decoder
...
Also, uncomment the `stc` test vectors (since the new decoder decodes
these properly) and comment out an instruction which looks suspiciously
like -6.0 in hex.
This also switches the parser back to `atomic.b.op` from `atomic.op.b`
which was a short-term workaround to make it easier for the legacy
disassembler.
Also switch the binary encoding for ldib to clear b0, because the new
disassembler warns about unexpected dontcare bits (which cases the
disasm to not match).
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
704e49bae0
freedreno/hw/isa: Add expression caching
...
Drops decoding an ~850KB collection of instructions from ~4min to ~1sec.
Granted for normal sized shaders, this probably doesn't matter.. but it
at reduces my cycle time for fixing things to match existing disasm
syntax using this massive collection of unique instructions.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
6d94f575d2
freedreno/hw/isa: Add description of ir3 ISA
...
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
e7630ec278
freedreno/hw: Add isaspec mechanism for documenting/defining an ISA
...
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
6309c9313b
freedreno/ir3: Add some new "logical" opcodes
...
Once we switch over to the xml based ir3 ISA definition, the opcodes
will be decoupled from instruction encoding. Which will let us better
handle cases where a single "opcode" (from instruction encoding stand-
point) means different things on different generations. And also cases
like the different variations of `b`ranch instructions, which share a
single hw "opcode" plus a separate "brtype" field. When we start using
these in ir3, we'd like to treat them as separate instructions and not
have to care about the details of how they are encoded.
For now, these are only used internally within the new xml generated
instruction encoding, but once the existing "packed struct" encoding/
decoding is replace, we'll update ir3 to start using the new opcode
enums directly (except for the `mov` variants).
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
cd31bface8
freedreno/ir3: Decouple ir3_info collection from assembler
...
We'll want to re-use this when cutting over to the new XML based
instruction encoding. So untangle it from instruction packing.
Also, move handling of the appended constant data out of the
assembler, since this isn't much related to instruction encoding.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
e1f8aaf9d2
freedreno/ir3: Fix ldg decoding/parsing
...
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997 >
2021-01-13 18:32:47 +00:00
b603875482
aco/ra: Use PhysRegInterval for count_zero
...
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
c30e83cc51
aco/ra: Use PhysRegInterval for collect_vars parameters
...
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
0959b7c435
aco/ra: Use PhysReg when indexing into RegisterFile's containers
...
This gets rid of a lot of implicit/explicit conversions from PhysReg to
unsigned.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
c3660f4781
aco/ra: Use PhysReg for member functions of PhysRegInterval
...
This replaces the various PhysReg{lb} casts that had been all over the place.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
d2d0096c0c
aco/ra: Remove unused function parameter
...
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
d9e1375e27
aco/ra: Use std::all_of to simplify a loop
...
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
f7e6b61379
aco/ra: Add helpers to test for intersection/containment of reg intervals
...
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
88f21ad87a
aco/ra: Move commonly repeated code to a helper function
...
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
8962510e38
aco/ra: Conservatively refactor get_reg_specified to use PhysRegInterval
...
All expressions have been replaced by their closest equivalent. No major
simplification efforts have been made to minimize risk of regressions.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
46c9d76134
aco/ra: Use std::all_of to simplify a loop
...
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
2b3b2f7ff5
aco/ra: Use std::find_if(_not) to clean up get_reg_simple
...
This makes for a more self-describing iteration behavior, and it gets rid
of the need for the duplicated "final check" at the bottom.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
ebdb362937
aco/ra: Add iterator interface for PhysRegInterval
...
This enables various loops to use range-based for.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799 >
2021-01-13 18:21:06 +00:00
Eric Anholt