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Author SHA1 Message Date
Alyssa Rosenzweig 49a89911c4 nir/print: do not print empty lists on intrinsics 
before:

  32     %0 = @load_vertex_id () ()

after:

   32     %0 = @load_vertex_id

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27925>
 2024-03-12 19:00:26 +00:00
Alyssa Rosenzweig ec9b6b5cfa util: add _mesa_hash_table_u64_num_entries 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27925>
 2024-03-12 19:00:26 +00:00
Alyssa Rosenzweig a6123a80da nir/opt_shrink_vectors: shrink some intrinsics from start 
If the backend supports it, intrinsics with a component() are straightforward to
shrink from the start. Notably helps vectorized I/O.

v2: add an option for this and enable only on grown up backends, because some
backends ignore the component() parameter.

RADV GFX11:
Totals from 921 (1.16% of 79439) affected shaders:
Instrs: 616558 -> 615529 (-0.17%); split: -0.30%, +0.14%
CodeSize: 3099864 -> 3095632 (-0.14%); split: -0.25%, +0.11%
Latency: 2177075 -> 2160966 (-0.74%); split: -0.79%, +0.05%
InvThroughput: 299997 -> 298664 (-0.44%); split: -0.47%, +0.02%
VClause: 16343 -> 16395 (+0.32%); split: -0.01%, +0.32%
SClause: 10715 -> 10714 (-0.01%)
Copies: 24736 -> 24701 (-0.14%); split: -0.37%, +0.23%
PreVGPRs: 30179 -> 30173 (-0.02%)
VALU: 353472 -> 353439 (-0.01%); split: -0.03%, +0.02%
SALU: 40323 -> 40322 (-0.00%)
VMEM: 25353 -> 25352 (-0.00%)

AGX:

total instructions in shared programs: 2038217 -> 2038049 (<.01%)
instructions in affected programs: 10249 -> 10081 (-1.64%)

total alu in shared programs: 1593094 -> 1592939 (<.01%)
alu in affected programs: 7145 -> 6990 (-2.17%)

total fscib in shared programs: 1589254 -> 1589102 (<.01%)
fscib in affected programs: 7217 -> 7065 (-2.11%)

total bytes in shared programs: 13975666 -> 13974722 (<.01%)
bytes in affected programs: 65942 -> 64998 (-1.43%)

total regs in shared programs: 592758 -> 591187 (-0.27%)
regs in affected programs: 6936 -> 5365 (-22.65%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v1)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28004>
 2024-03-12 18:17:17 +00:00
Alyssa Rosenzweig aa99753a28 nir/opt_shrink_vectors: hoist alu helpers 
to be used earlier in the file in the next commit

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28004>
 2024-03-12 18:17:17 +00:00
José Roberto de Souza d1916432ab intel/dev: Nuke display_ver 
It is not used.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28128>
 2024-03-12 17:44:46 +00:00
José Roberto de Souza b09ffe48f2 intel/dev: Nuke 'ver == 10' check 
There is no intel_device_info with ver 10 anymore.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28128>
 2024-03-12 17:44:46 +00:00
Rhys Perry a977a51a21 radv: stop using 5/8 component SSBO stores 
These apparently work, but I'm not sure they were supposed to.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28108>
 2024-03-12 17:23:29 +00:00
Rhys Perry cc7e3efc7c radv: don't advertise DGC with LLVM 
The meta shaders for this feature don't compile with LLVM because of 5/8
component SSBO stores. I'm not sure this was ever expected to work.

This seemed to break vkd3d-proton.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28108>
 2024-03-12 17:23:29 +00:00
Christian Gmeiner 3409c60099 etnaviv: isa: Support multiple encodings for texldb 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 20678b9204 etnaviv: isa: Fix #instruction-tex-src0-src1-src2 bitset 
src1 got wrong values.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner ccc99bd42d etnaviv: isa: Support multiple encodings for texldl 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 8d117b46ea etnaviv: isa: Support unary texkill instruction 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 86de104d07 etnaviv: isa: Support unary branch instruction 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 0aa737018e etnaviv: isa: Combine branch and branch_if 
As we want to use the new asm as a drop-in replacement we
need to combine branch and branch_if back to one bitset.

This is caused by the fact that we need to replicate the defines
in isa.xml.h.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 48e1589b44 etnaviv: isa: Correct #instruction-alu-no-dst-has-src0-src1 expr name 
This expression only checks if src0 and src1 are in use.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 10a7cf3121 etnaviv: isa: Correct #instruction-alu-no-dst-maybe-src1-src2 name 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner dfb2fcf652 etnaviv: isa: Correct #instruction-cf-src1-src2 bitset name 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner c2ffc7a09b etnaviv: isa: Correct SRC0_AMODE 
It is 3 bit long and not one.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner b1cbd35bb5 etnaviv: isa: Move {TEX_SWIZ} 
Should have never been there.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner d8f6de7314 etnaviv: isa: Add movar opcode 
I was unable to grab this opcode from blob, so lets just
document it as the Gallium driver makes use of it.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner e77fbe2bcc etnaviv: isa: Add internal register group 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner f416bb3f8c etnaviv: isa: Rename reg_group u2 to u 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner cf3fa2fd8c etnaviv: isa: Reorder instructions 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 9c6378abec etnaviv: isa: Add div opcode 
Encoded instruction is taken from blob running the following CL kernel:

 __kernel void simple(__global float *out, __global float *in)
{
    int iGID = get_global_id(0);
    out[iGID] = 4.5f / in[iGID];
}

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner e2a9bc73f5 etnaviv: isa: Remove note about GC3000 
All the encoded instructions in the Opcodes test are comming
from blob running on different GPU models.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner fa3d2bc486 etnaviv: isa: Add texldd opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.shaders.texture_functions.texturegrad.sampler2d_float_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 0701f3ef9b etnaviv: isa: Add texldl opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.shaders.texture_functions.texturegrad.isampler2d_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 8c86bd0209 etnaviv: isa: Add texldb opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.texture.mipmap.2d.bias.linear_nearest

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 3c72596ebf etnaviv: isa: Add bit_rev opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.int_lowp_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 2e2a0e8059 etnaviv: isa: Add movai opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.shaders.struct.uniform.dynamic_loop_struct_array_fragment

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 73584cf46a etnaviv: isa: Name cond enum value 22 
Blob told me about it when running:
- dEQP-GLES3.functional.ubo.random.scalar_types.4

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:44 +00:00
Christian Gmeiner 20022f5389 etnaviv: isa: Add branch_any opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic.bvec3_api_int_both

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:43 +00:00
Christian Gmeiner 6a71636179 etnaviv: isa: Correct dp2 opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES2.functional.shaders.operator.geometric.refract.highp_vec2_float_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:43 +00:00
Christian Gmeiner 47106e0f80 etnaviv: isa: Add bit_extract opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.int_lowp_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:43 +00:00
Christian Gmeiner 3b4cbbf0d2 etnaviv: isa: Add norm_dp2, norm_dp3 and norm_dp4 opcodes 
Encoded instructions are taken from blob running:
- dEQP-GLES2.functional.shaders.operator.geometric.normalize.mediump_vec2_vertex
- dEQP-GLES2.functional.shaders.operator.geometric.normalize.mediump_vec3_vertex
- dEQP-GLES2.functional.shaders.operator.geometric.normalize.mediump_vec4_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:43 +00:00
Christian Gmeiner 4cd779af3f etnaviv: isa: Add frc opcode 
Encoded instruction is taken from blob running:
- dEQP-GLES2.functional.shaders.operator.common_functions.fract.mediump_vec4_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:43 +00:00
Christian Gmeiner ede0008c16 etnaviv: isa: Add dsx and dsy opcodes 
Encoded instructions are taken from blob running:
- dEQP-GLES3.functional.shaders.derivate.dfdx.texture.basic.float_highp
- dEQP-GLES3.functional.shaders.derivate.dfdy.texture.basic.float_highp

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:43 +00:00
Christian Gmeiner 031c2c26df etnaviv: isa: Remove duplicate #instruction-alu-atomic 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
 2024-03-12 17:02:43 +00:00
Mike Blumenkrantz 0f66589c2a mesa: force rendertarget usage on required-renderable formats 
the existing guesswork during format selection for teximage is
accurate most of the time, but it's not accurate all of the time.
GL/ES each have a set of sized formats that are required to be
color renderable, and so any time one of these is allocated as a
texture, it MUST have the rendertarget usage bit attached so that
it can later be bound as a framebuffer attachment

an alternative might be to relax this and then try to do migration
to a different format/buffer later if necessary, but that's hard and
probably not actually as useful

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28055>
 2024-03-12 14:22:17 +00:00
Erik Faye-Lund d7def3ccdf panfrost: add pan_force_afbc_packing driconf 
This is useful for forcing AFBC-P to be used in applications where it's
know to work well. This can significantly reduce memory consumption and
bandwidth, leading more applications working in the first place, and
also better performance.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27916>
 2024-03-12 12:44:49 +00:00
Erik Faye-Lund 2bcdc4939c panfrost: add driconf infrastructure 
This is the boiler-plate code needed to support driver-specific driconf
variables in Panfrost.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27916>
 2024-03-12 12:44:49 +00:00
Erik Faye-Lund d861bd1563 panfrost: give afbc-packing its own flag 
There's no point in querying this over and over again for each
resource, especially not when this test is about to become more
complicated. So let's give this its own flag.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27916>
 2024-03-12 12:44:49 +00:00
Karol Herbst 7487ac2046 rusticl/device: support query_memory_info to retrieve available memory 
Some drivers implement query_memory_info, but not the MAX_GLOBAL_SIZE
compute cap.

Long term we should drop the compute cap anyway.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28122>
 2024-03-12 12:24:31 +00:00
Karol Herbst 2df640c4f6 rusticl/kernel: assign sampler locations before DCEing variables 
This fixes an issue hit by one of darktable's kernels, where the sampler
argument got assigned the location of a dead kernel parameter turning it
into a zombie and leading us to trash the kernel input buffer's layout.

Fixes: 25b8a34b48 ("rusticl/kernel: inline samplers")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28121>
 2024-03-12 11:30:48 +01:00
Tapani Pälli 493d5764e3 iris: setup distribution granularity with Wa_14019166699 
Workaround describes that we need to set instance level distribution
granularity when primitive id is used by the draw.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27955>
 2024-03-12 09:25:32 +00:00
Tapani Pälli da3d5d1064 iris: refactor function that checks primitive id usage 
We will need this for another workaround, make it more generic.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27955>
 2024-03-12 09:25:32 +00:00
Tapani Pälli 275bcbd7a7 anv: setup distribution granularity with Wa_14019166699 
Workaround describes that we need to set instance level distribution
granularity when primitive id is used by the draw.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27955>
 2024-03-12 09:25:32 +00:00
Lionel Landwerlin 75c6ad9907 intel/fs: fixup sampler header message 
If you look at the sampler message header on Gfx9+, you'll see that we
mostly only use 2 dwords (dw2 & dw3). DW2 has a bunch of sampler
parameters, DW3 is the sampler handle.

On Gfx9 we can micro optimize by copying r0 into the header because
the HW mostly doesn't care about other DWs. We just have to clear dw2
on non VS/FS stages.

On Gfx11+, we always have to do a careful copy of the r0.3 bits to
mask out the bottom unrelated bits. So there, just clearing the entire
header makes more sense.

On Xe2+, the dw4 of the header references the sampler feedback surface
handle and bit0 is a boolean to know whether to use that surface or
not. So it *REALLY* matters to have that as 0. If we copy r0, we'll
get random bits in dw4, leading to enable that surface.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28082>
 2024-03-12 07:25:45 +00:00
Hyunjun Ko db8eaa3620 anv/video: fix scan order for scaling lists on H265 decoding. 
The default scan order of scaling lists is up-right-diagonal
according to the spec. But the device requires raster order,
so we need to convert from the passed scaling lists.

Fixes: 8d519eb ("anv: add initial video decode support for h265")

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28063>
 2024-03-12 03:33:49 +00:00
Timothy Arceri 182bff5c05 glsl: remove unrequired do_lower_jumps() call 
We were using this to remove unreachable instructions following
jumps. The previous patch allowed glsl to nir to handle these
instructions so this call is no longer needed.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27288>
 2024-03-12 01:43:03 +00:00