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etnaviv: isa: Add frc opcode

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Encoded instruction is taken from blob running:
- dEQP-GLES2.functional.shaders.operator.common_functions.fract.mediump_vec4_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
This commit is contained in:
Christian Gmeiner
2024-02-27 10:09:56 +01:00
committed by Marge Bot
parent ede0008c16
commit 4cd779af3f
2 changed files with 5 additions and 1 deletions
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src/etnaviv/isa/etnaviv.xml
+4 -1
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@@ -951,7 +951,10 @@ SPDX-License-Identifier: MIT
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<!-- frc -->
<bitset name="frc" extends="#instruction-alu-src2">
<pattern low="0" high="5">010011</pattern> <!-- OPC -->
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="call" extends="#instruction-cf-no-src">
<pattern low="0" high="5">010100</pattern> <!-- OPC -->
src/etnaviv/isa/tests/disasm.cpp
+1
View File
@@ -105,6 +105,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest,
disasm_state{ {0x008010d0, 0x00000800, 0x00000040, 0x00000002}, "set.ge.pack t0.x___, t0.xxxx, u0.xxxx, void\n" },
disasm_state{ {0x01001011, 0x00000004, 0x00000000, 0x00154008}, "exp t0._y__, void, void, t0.yyyy\n" },
disasm_state{ {0x01801012, 0x00000005, 0x00000000, 0x00000008}, "log.rtz t0.xy__, void, void, t0.xxxx\n" },
disasm_state{ {0x07811013, 0x00000004, 0x00000000, 0x000e4018}, "frc t1, void, void, t1.yzwx\n" },
disasm_state{ {0x00000014, 0x00000000, 0x00000000, 0x00000380}, "call void, void, void, 7\n" },
disasm_state{ {0x00000015, 0x00000000, 0x00000000, 0x00000000}, "ret void, void, void, void\n" },
disasm_state{ {0x00000016, 0x00000000, 0x00000000, 0x00001080}, "branch void, void, void, 33\n"},