From 4cd779af3f69a45eca74be454e6b70fc1c85312b Mon Sep 17 00:00:00 2001
From: Christian Gmeiner <cgmeiner@igalia.com>
Date: Tue, 27 Feb 2024 10:09:56 +0100
Subject: [PATCH] etnaviv: isa: Add frc opcode

Encoded instruction is taken from blob running:
- dEQP-GLES2.functional.shaders.operator.common_functions.fract.mediump_vec4_vertex

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
---
 src/etnaviv/isa/etnaviv.xml      | 5 ++++-
 src/etnaviv/isa/tests/disasm.cpp | 1 +
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/etnaviv/isa/etnaviv.xml b/src/etnaviv/isa/etnaviv.xml
index b9827f1d00e..e0c8b53eb5a 100644
--- a/src/etnaviv/isa/etnaviv.xml
+++ b/src/etnaviv/isa/etnaviv.xml
@@ -951,7 +951,10 @@ SPDX-License-Identifier: MIT
 	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
 
-<!-- frc -->
+<bitset name="frc" extends="#instruction-alu-src2">
+	<pattern low="0" high="5">010011</pattern> <!-- OPC -->
+	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
+</bitset>
 
 <bitset name="call" extends="#instruction-cf-no-src">
 	<pattern low="0" high="5">010100</pattern> <!-- OPC -->
diff --git a/src/etnaviv/isa/tests/disasm.cpp b/src/etnaviv/isa/tests/disasm.cpp
index 10a7df35d91..38c47f79236 100644
--- a/src/etnaviv/isa/tests/disasm.cpp
+++ b/src/etnaviv/isa/tests/disasm.cpp
@@ -105,6 +105,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest,
       disasm_state{ {0x008010d0, 0x00000800, 0x00000040, 0x00000002}, "set.ge.pack       t0.x___, t0.xxxx, u0.xxxx, void\n" },
       disasm_state{ {0x01001011, 0x00000004, 0x00000000, 0x00154008}, "exp               t0._y__, void, void, t0.yyyy\n" },
       disasm_state{ {0x01801012, 0x00000005, 0x00000000, 0x00000008}, "log.rtz           t0.xy__, void, void, t0.xxxx\n" },
+      disasm_state{ {0x07811013, 0x00000004, 0x00000000, 0x000e4018}, "frc               t1, void, void, t1.yzwx\n" },
       disasm_state{ {0x00000014, 0x00000000, 0x00000000, 0x00000380}, "call              void, void, void, 7\n" },
       disasm_state{ {0x00000015, 0x00000000, 0x00000000, 0x00000000}, "ret               void, void, void, void\n" },
       disasm_state{ {0x00000016, 0x00000000, 0x00000000, 0x00001080}, "branch            void, void, void, 33\n"},