intel/fs: fixup sampler header message
If you look at the sampler message header on Gfx9+, you'll see that we mostly only use 2 dwords (dw2 & dw3). DW2 has a bunch of sampler parameters, DW3 is the sampler handle. On Gfx9 we can micro optimize by copying r0 into the header because the HW mostly doesn't care about other DWs. We just have to clear dw2 on non VS/FS stages. On Gfx11+, we always have to do a careful copy of the r0.3 bits to mask out the bottom unrelated bits. So there, just clearing the entire header makes more sense. On Xe2+, the dw4 of the header references the sampler feedback surface handle and bit0 is a boolean to know whether to use that surface or not. So it *REALLY* matters to have that as 0. If we copy r0, we'll get random bits in dw4, leading to enable that surface. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Rohan Garg <rohan.garg@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28082>
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@@ -788,10 +788,14 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
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/* Build the actual header */
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const fs_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0);
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const fs_builder ubld1 = ubld.group(1, 0);
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ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
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if (devinfo->ver >= 11)
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ubld.MOV(header, brw_imm_ud(0));
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else
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ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
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if (inst->offset) {
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ubld1.MOV(component(header, 2), brw_imm_ud(inst->offset));
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} else if (bld.shader->stage != MESA_SHADER_VERTEX &&
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} else if (devinfo->ver < 11 &&
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bld.shader->stage != MESA_SHADER_VERTEX &&
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bld.shader->stage != MESA_SHADER_FRAGMENT) {
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/* The vertex and fragment stages have g0.2 set to 0, so
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* header0.2 is 0 when g0 is copied. Other stages may not, so we
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