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Author SHA1 Message Date
Mary Guillemard b0fa3fda3a panvk: Skip dispatch on empty workgroup 
Fix "dEQP-VK.compute.pipeline.basic.empty_workgroup_*" crashes.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29872>
 2024-06-26 16:33:40 +00:00
Danylo Piliaiev 653a4dc58f freedreno: Use LRZ feedback in gmem 
(Same as in Turnip)

We set LRZ_FEEDBACK_EARLY_LRZ_LATE_Z mask for rendering pass after
HW binning because:
- Draws with EARLY_Z contributed to depth buffer in BINNING stage;
- Draws with LATE_Z is what usually disables LRZ.
- Draws with EARLY_LRZ_LATE_Z are the ones we want because they
  represent the common case of FS with "discard".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
 2024-06-26 15:53:51 +00:00
Danylo Piliaiev 02b1d23fed tu: Enable LRZ feedback in sysmem 
The perf benefits are to be observed but that's what blob is doing.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
 2024-06-26 15:53:51 +00:00
Danylo Piliaiev 2a33cd113a tu: Use LRZ feedback in gmem 
We set LRZ_FEEDBACK_EARLY_LRZ_LATE_Z mask for rendering pass after
HW binning because:
- Draws with EARLY_Z contributed to depth buffer in BINNING stage;
- Draws with LATE_Z is what usually disables LRZ.
- Draws with EARLY_LRZ_LATE_Z are the ones we want because they
  represent the common case of FS with "discard".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
 2024-06-26 15:53:51 +00:00
Danylo Piliaiev 04e18dc96f freedreno/devices: Define and appropriately set has_lrz_feedback 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
 2024-06-26 15:53:51 +00:00
Danylo Piliaiev 229bd7b9b9 freedreno: Describe LRZ feedback mechanism 
Some draws do write depth but cannot contribute to LRZ during the BINNING pass
e.g. when fragment shader has "discard" in it, however they can contribute to
LRZ during the RENDERING pass via LRZ feedback meachanism. This may allow the
draws that follow to depth test against the updated LRZ, this is especially
important if such "bad" draws were at the start of the renderpass.

LRZ feedback happens during the RENDERING pass when LRZ_FEEDBACK_ZMODE_MASK
is set, if draw has a6xx_ztest_mode that has corresponding flag set in
LRZ_FEEDBACK_ZMODE_MASK - its depth values would be used for feedback.

LRZ feedback alongside with LRZ testing also works during sysmem rendering.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
 2024-06-26 15:53:51 +00:00
Connor Abbott 78c5daf029 tu: Add early preamble statistic 
It can affect performance if we accidentally disable early preamble so
record it here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29903>
 2024-06-26 15:16:38 +00:00
Connor Abbott 337fb7dec2 ir3, tu, freedreno: Move early_preamble to ir3_shader 
The ir3_info is reset by ir3_collect_shader_info() on the expectation
that all info is collected inside that function. This meant that we were
accidentally disabling early preamble. Re-enable it.

We keep a copy in ir3_info for shader statistics in the next commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29903>
 2024-06-26 15:16:38 +00:00
Connor Abbott 293f137d4d freedreno: Disable early preamble on a6xx gen4 
Disable it until someone does more investigation of exactly what needs
to be disabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29903>
 2024-06-26 15:16:38 +00:00
Connor Abbott c42f6597f9 ir3: Make sure constlen includes stc/ldc.k/ldg.k instructions 
nir_opt_preamble sometimes adds useless expressions, in which case we
may have stc instructions and no corresponding use of the constant.
Things can go sideways when these aren't included in the constlen, so
far only observed when earlypreamble is enabled.

Fixes: ccc64b7e00 ("ir3: Plumb through store_uniform_ir3 intrinsic")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29903>
 2024-06-26 15:16:38 +00:00
Matt Coster 536775ee8b docs: List VK_EXT_debug_utils 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24488>
 2024-06-26 15:07:16 +00:00
Valentine Burley 8cfdc099cd tu: Use the common version of vkQueueBindSparse 
This is implemented in the common runtime. No need to provide a stub here.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29854>
 2024-06-26 14:38:22 +00:00
Valentine Burley d882198fc3 tu: Move buffer related code to tu_buffer.cc/h 
More code isolation. Match the structure of the common Vulkan runtime,
NVK and RADV.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29854>
 2024-06-26 14:38:22 +00:00
Valentine Burley c0a9b0f8d6 tu: Use the common version of vkGetBufferMemoryRequirements2 
Additionally simplify the code by inlining the logic from
tu_get_buffer_memory_requirements directly into
tu_GetDeviceBufferMemoryRequirements.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29854>
 2024-06-26 14:38:22 +00:00
Pierre-Eric Pelloux-Prayer 1a06494e65 radeonsi/tests: clarify the output when results changes 
Print up to 10 results that are different from the baseline:

   2 new results:
     * spec@!opengl 1.0@rasterpos,Crash
     * spec@glsl-es-3.00@execution@built-in-functions@vs-packhalf2x16,Fail

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer d9f150f18b radeonsi/tests: update tests baseline 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer 6ec95b990e ac/nir: don't use the compute blit for PIPE_FORMAT_R5G6B5_UNORM 
It breaks spec@arb_pixel_buffer_object@texsubimage array pbo and
spec@arb_pixel_buffer_object@texsubimage pbo with some formats:

72,3,0: test = 140,0,8,255 ref = 148,0,8,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_R3_G3_B2
  region: 5, 3  116 x 11
72,3,0: test = 140,0,8,255 ref = 148,0,8,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_RGB5
  region: 33, 3  78 x 11
72,10,0: test = 140,0,41,255 ref = 148,0,41,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_RGB5_A1
  region: 3, 10  124 x 33
72,19,4: test = 140,65,74,255 ref = 148,65,74,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_R3_G3_B2
  region: 36, 19  81 x 18
12,36,4: test = 25,66,140,255 ref = 25,66,148,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_RGB5
  region: 12, 9  30 x 39
72,22,2: test = 140,33,90,255 ref = 148,33,90,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_RGB5_A1
  region: 39, 22  36 x 37

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer c97591b862 radeonsi: add gfx11 workaround for upgraded_depth 
For unknown reasons, this is needed to avoid breaking
a bunch of tests:

   .*tex-miplevel-selection.*
   KHR-GL46.direct_state_access.framebuffers_texture_attachment,Fail
   KHR-GL46.direct_state_access.framebuffers_texture_layer_attachment,Fail
   .*.core.texture_cube_map_array.sampling

These failures were previously hidden by extra flushes in the
blitter that were removed in 969ed851.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer abd048124a ac/surface: reject modifiers with retile_dcc and bpe != 32 
radv has a comment in radv_meta_dcc_retile.c:
   * BPE is always 4 at the moment and the rest is derived from the tilemode.
radeonsi has in si_retile_dcc:
   /* We have only 1 variant per bpp for now, so expect 32 bpp. */
   assert(tex->surface.bpe == 4);

This fixes ext_image_dma_buf_import-modifiers for radeonsi.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer 9d8073a5fd radeonsi/tests: add a shortcut to re-run only failing tests 
'-t baseline' will only run the tests that are marked as failing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer 27a841d335 radeonsi/tests: don't match gfx10_3 baseline for gfx10 family 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer 19e342b877 radeonsi: handle DBG(TEX) after tc_compatible_htile is set 
Otherwise the value printed might be incorrect.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Erik Faye-Lund f4e7204e73 docs: fix bootstrap-extension 
We shouldn't use this extension at all if we're not using the HTML
builder. This should hopefully fix this issue a bit more fundamentally.

This caused issues when using the spelling extension, something I do
locally from time to time.

Fixes: f72033bb70 ("docs: add bootstrap extension")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29888>
 2024-06-26 13:54:13 +00:00
Erik Faye-Lund 18db05d3e6 vulkan/runtime: implementaiton -> implementation 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund 3967f8cd84 vulkan/runtime: multiesample -> multisample 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund 788d1b5a67 vulkan/runtime: abreviation -> abbreviation 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund 947446ade7 vulkan/runtime: initizlie -> initialize 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund a966a11161 vulkan/runtime: tne -> the 
This is clearly a typo.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Karol Herbst e5bb32da98 rusticl: enable v3d 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 0b85476d86 v3d: never replace a mapped bo 
The application might have a pointer into the mapped bo.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst e5c4ea9323 v3d: fix MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 6768c81974 v3d: support variable shared memory 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 61b1a14e91 v3d: lower 64 bit ALUs 
Even though rusticl won't advertise support for 64 bit ints, some of the
libclc builtins still use 64 bit operations to lower 32 bit ALU ops.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 7ff96fb5b0 v3d: lower CL alus 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 8f72e60c75 v3d: treat SHADER_KERNEL as SHADER_COMPUTE 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 3889a8e26c v3d: implement gallium APIs for OpenCL support 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 742984a325 broadcom/compiler: handle variable shared memory 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 9bf0b3a112 broadcom/compiler: call nir_lower_64bit_phis 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst 4a169a518e broadcom/compiler: implement load_kernel_input 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst caa3872f76 broadcom/compiler: abort on unknown intrinsics 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst f8ab9c0e93 broadcom/compiler: handle up to vec16 load_uniforms 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst e050b13777 broadcom/compiler: try handling 8/16 bit alu operations 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst c7f9cca985 broadcom/compiler: fix iu2f32 for 8 and 16 bit inputs 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst 214121e9b0 broadcom/compiler: handle fp16 conversion ops 
As long as fp16 isn't advertized it's not doing much, but it also doesn't
hurt to add them.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst c2ec65eeda broadcom/compiler: add generated v3d_nir_lower_algebraic 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst a8f4ff691b rusticl/kernel/launch: fix global work offsets for 32 bit archs again 
Fixes: bb2453c649 ("rusticl/kernel: move most of the code in launch inside the closure")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst 39721a7476 rusticl/mesa/screen: handle get_timestamp not set by driver 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst bb33dbeeaa rusticl/mesa/context: handle clear_buffer not set by driver 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst be4f3c2aa8 rusticl/device: require PIPE_CAP_TEXTURE_SAMPLER_INDEPENDENT for image support 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst 0fa4eaf6f6 gallium: add PIPE_CAP_TEXTURE_SAMPLER_INDEPENDENT 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00