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tu: Use LRZ feedback in gmem

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We set LRZ_FEEDBACK_EARLY_LRZ_LATE_Z mask for rendering pass after
HW binning because:
- Draws with EARLY_Z contributed to depth buffer in BINNING stage;
- Draws with LATE_Z is what usually disables LRZ.
- Draws with EARLY_LRZ_LATE_Z are the ones we want because they
  represent the common case of FS with "discard".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
This commit is contained in:
Danylo Piliaiev
2023-09-21 18:39:38 +02:00
committed by Marge Bot
parent 04e18dc96f
commit 2a33cd113a
1 changed files with 26 additions and 15 deletions
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src/freedreno/vulkan/tu_cmd_buffer.cc
+26 -15
View File
@@ -1952,20 +1952,27 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
{
.render_mode = BINNING_PASS,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z),
.lrz_feedback_zmode_mask =
phys_dev->info->a6xx.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
: LRZ_FEEDBACK_NONE
});
tu6_emit_render_cntl<CHIP>(cmd, cmd->state.subpass, cs, true);
tu6_emit_binning_pass<CHIP>(cmd, cs);
tu6_emit_bin_size<CHIP>(cs, tiling->tile0.width, tiling->tile0.height,
{
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = true,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z),
});
tu6_emit_bin_size<CHIP>(
cs, tiling->tile0.width, tiling->tile0.height,
{
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !phys_dev->info->a6xx.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
phys_dev->info->a6xx.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
: LRZ_FEEDBACK_NONE,
});
tu_cs_emit_regs(cs,
A6XX_VFD_MODE_CNTL(RENDERING_PASS));
@@ -1983,13 +1990,17 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_LOCAL, 1);
tu_cs_emit(cs, 0x1);
} else {
tu6_emit_bin_size<CHIP>(cs, tiling->tile0.width, tiling->tile0.height,
{
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = true,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z),
});
tu6_emit_bin_size<CHIP>(
cs, tiling->tile0.width, tiling->tile0.height,
{
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !phys_dev->info->a6xx.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
phys_dev->info->a6xx.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z
: LRZ_FEEDBACK_NONE,
});
if (tiling->binning_possible) {
/* Mark all tiles as visible for tu6_emit_cond_for_load_stores(), since