216491 Commits

Author SHA1 Message Date
Luca Mignatti a325151787 macOS: Add portable libGL wrapper and fix library path discovery
- Add glwrapper subdirectory to build system for libgl_interpose.dylib and libGL.dylib
- Make libgl_interpose.c and libgl_wrapper.c use dladdr() to find libEGL relative to themselves
- Add MESA_EGL_LIBRARY and MESA_VULKAN_LIBRARY env var support for bypassing SIP's stripping of DYLD_LIBRARY_PATH
- Zink now checks MESA_VULKAN_LIBRARY before default VK_LIBNAME

This enables Mesa to work on macOS when DYLD_LIBRARY_PATH is stripped by System Integrity Protection, as happens with Java processes.
2026-01-02 11:17:31 -06:00
Luca Mignatti f9624417ea zink/egl: performance optimizations for KosmicKrisp on Metal
- Disable implicit_sync for KosmicKrisp to avoid per-frame GPU stall
- Cache drawable size instead of dispatch_sync to main thread
- Remove debug crash handler overhead
2025-12-31 13:05:19 -06:00
Luca Mignatti 03a56f0032 zink/kopper: fix window resizing on Metal surfaces 2025-12-31 12:10:39 -06:00
Luca Mignatti e0c225a3af kosmickrisp: remove debug fprintf from kk_CmdBlitImage2 2025-12-30 18:44:07 -06:00
Luca Mignatti 9a50f64b64 Remove debug fprintf statements
Removes DEBUG fprintf statements from:
- kk_image_view.c (sampled_gpu_resource_id logging)
- platform_surfaceless.c (get_drawable_info and Metal layer logging)
- Orphaned continuation lines from previous sed cleanup

Also forces VK_COMPOSITE_ALPHA_OPAQUE_BIT_KHR in zink_kopper.c and
present_opaque=true in platform_surfaceless.c (attempts to fix
hotbar translucency, but issue persists).
2025-12-30 18:25:05 -06:00
Luca Mignatti 1812ec4190 egl/surfaceless: set CAMetalLayer as opaque and remove debug logging
Fix hotbar and UI translucency on Metal by setting the CAMetalLayer to be
opaque via [layer setOpaque:YES]. Without this, the Metal compositor blends
the layer's alpha channel with the desktop background, causing translucent
UI elements.

Also removes all DEBUG fprintf statements from platform_surfaceless.c that
were added during debugging.
2025-12-30 18:13:57 -06:00
Luca Mignatti eb364234f9 kosmickrisp/zink: fix gray screen on Metal by forcing alpha=1 in blit shaders
Minecraft and other applications can render with alpha=0 in the backbuffer,
which causes the content to appear transparent/gray when blitted to the
Metal swapchain (CAMetalLayer). This is because Metal's compositor respects
the alpha channel of the swapchain content.

Fix this by forcing the alpha channel to 1.0 in both blit shader paths:
- vk_meta_blit_resolve.c: For the meta blit path (vk_meta_blit_image2)
- u_simple_shaders.c: For the util_blitter path

Additionally, force format conversion blits (RGBA->BGRA) to use util_blitter
instead of vk_meta_blit, as the meta path has intermittent black flashing
issues on Metal that still need investigation.

Also removes debug fprintf statements added during debugging.
2025-12-30 13:30:36 -06:00
Luca Mignatti fc578131ad Fix gray screen: Force alpha=1 in vk_meta_blit for Metal/kosmickrisp
The gray screen issue was caused by Minecraft's FBO having alpha=0 for
3D world areas. When blitting to the swapchain, these areas appeared
transparent/gray on Metal.

Key changes:
- vk_meta_blit_resolve.c: Force alpha channel to 1.0 for color blits
- zink_blit.c: Allow format conversion in blit_native (commented out rejection)
- kk_cmd_meta.c: Add kk_cmd_buffer_dirty_all_gfx in begin/end for clean state
- Added debug logging throughout blit path (to be cleaned up later)

Main menu now renders correctly. In-game still has flashing issue to debug.
2025-12-30 13:12:11 -06:00
Luca Mignatti 3ce192bd3c Fix Minecraft/Zink on macOS with EGL/Kopper Metal support
Key fixes:
- platform_surfaceless.c: Add macOS Metal window surface support for Kopper
  - Replace NSViewBackingLayer with CAMetalLayer for proper Metal rendering
  - Set drawableSize explicitly to avoid 1x1 swapchain
  - Configure contentsScale for Retina display support
  - Dispatch UI operations to Main Thread to avoid race conditions

- zink_kopper.c: Add debug logging for swapchain creation/present

- kk_shader.c: Disable shader caching to fix stale Metal pointer crash
  - Cached Metal pipeline pointers are process-specific and can't be
    restored across sessions without full pipeline state

- Various debug logging additions throughout the codebase

Tested with Minecraft 1.21.11 on Apple M4 Pro, achieving 60fps.
2025-12-30 11:40:24 -06:00
Mary Guillemard ea4dedde8f hk: Advertise VK_KHR_pipeline_binary
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39095>
2025-12-28 09:41:17 +01:00
Mary Guillemard b34e113a40 hk: Uses vk_device::mem_cache
We had our own pipeline cache field, we need to use the common field
instead for VK_KHR_pipeline_binary.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39095>
2025-12-28 09:41:17 +01:00
Mary Guillemard c785c3c22d docs/features: Update info on VK_KHR_pipeline_binary
Was forgotten.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39095>
2025-12-28 09:41:17 +01:00
Mary Guillemard b8ae33be7c hk: Advertise VK_EXT_shader_uniform_buffer_unsized_array
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39095>
2025-12-28 09:41:17 +01:00
Mary Guillemard 860870ca4d docs/features: add anv to VK_EXT_shader_uniform_buffer_unsized_array
Was forgotten.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39095>
2025-12-28 09:41:17 +01:00
Sergi Blanch Torne 467dd0b990 ci,crnm: warning message when a job can't be enabled
Instead of an exception that completely stops the run'n'monitor process, when
a job with a specific status can't be enabled, just log it with a warning.
Don't attempt to enable it again unless it changes the status.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39049>
2025-12-27 20:24:28 +00:00
Sergi Blanch Torne a689ec8676 ci,crnm: enable attempts ctr include status
The counter about how many times a job has been tried to enable, can host the
information about the job status when these attempts happen. This groups the
attempts to separate unrelated differences between job statuses.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39049>
2025-12-27 20:24:28 +00:00
Sagar Ghuge d10d75bc93 anv: Add host barrier while dumping out BVH data
This patch adds compute_w_to_host_r barrier and also throw QueueWaitIdle
just to make sure all operations are completed before we fetch the BVH
data on the host.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39079>
2025-12-27 18:47:58 +00:00
Calder Young 7b74321640 anv: Fix load factor for batch buffer allocation
The entire range of the allocated bo up to bo->size will be used, even if
alloc_size was way less, so to track the growth precisely for load factoring,
the allocated_batch_size should increase by bo->size.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38703>
2025-12-26 20:44:18 +00:00
Calder Young 4de00e01dd anv: Fix valgrind errors on batch buffers allocated from bo_pool
Although a specific size is requested, the entire range of the returned bo up
to bo->size may end up being used by anv_batch_chain, spamming memcheck errors.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38703>
2025-12-26 20:44:18 +00:00
Adam Jackson 0d5db86eba iris: Stop hardcoding 0:2:0 for the PCI bus address
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33656>
2025-12-26 05:15:41 +00:00
Christian Gmeiner 68fb3a601c etnaviv: isa: Add assembler support for infinity and NaN immediates
Implement parsing and encoding of special floating-point values for
both 20-bit (f20) and 16-bit (f16) immediate formats:

  inf:f20   - Positive infinity (imm_val=0x7f800, imm_type=0)
  -inf:f20  - Negative infinity (imm_val=0xff800, imm_type=0)
  nan:f20   - Quiet NaN         (imm_val=0x7fc00, imm_type=0)
  -nan:f20  - Negative NaN      (imm_val=0xffc00, imm_type=0)

  inf:f16   - Positive infinity (imm_val=0x7c00, imm_type=3)
  -inf:f16  - Negative infinity (imm_val=0xfc00, imm_type=3)
  nan:f16   - Quiet NaN         (imm_val=0x7fff, imm_type=3)
  -nan:f16  - Negative NaN      (imm_val=0xffff, imm_type=3)

The f20 format stores the upper 20 bits of an IEEE 754 single-precision
float. The f16 format stores the 16-bit half-float value directly.

This enables round-trip assembly of shaders containing these special
values, which can appear in GPU command streams captured from the
proprietary driver.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39016>
2025-12-25 22:57:48 +00:00
Christian Gmeiner 59e30cc86d etnaviv: isa: Fix f16 immediate encoding
The previous code incorrectly treated f16 immediates as truncated f32
values (bits >> 12). The f16 immediate format (imm_type=3) expects a
16-bit IEEE 754 half-precision float, not the upper 20 bits of an f32.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39016>
2025-12-25 22:57:48 +00:00
Christian Gmeiner 3f1165a9ca etnaviv: isa: Remove dual16 mode parameter from parser API
The dual16 mode is now fully encoded in the disassembly output through
type suffixes (:f16 vs :f20) and register naming (th vs t), making the
explicit dual16 mode parameter redundant.

Previously, the parser needed a dual16_mode flag to determine whether
float immediates should use imm_type=0 (f32) or imm_type=3 (f16). Now
that the disassembler emits explicit :f16/:f20 suffixes, the parser can
determine the correct encoding directly from the input text.

This simplifies the API by removing the dual16_mode parameter from:
  - isa_parse_str()
  - isa_parse_file()
  - Internal parsing functions

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39016>
2025-12-25 22:57:47 +00:00
Christian Gmeiner 776c1a7039 etnaviv: isa: Add type suffixes to immediate value encoding
The assembler and disassembler now use explicit type suffixes for all
immediate values to ensure correct round-trip encoding:

  - :f20  - 20-bit float (upper 20 bits of IEEE 754 single precision)
  - :f16  - 16-bit half-float
  - :s20  - 20-bit signed integer (two's complement)
  - :u20  - 20-bit unsigned integer

Previously, the parser did not distinguish between signed and unsigned
integers, causing incorrect encoding. The signed format uses 20-bit
two's complement where bit 19 is the sign bit and maps to AMODE[0] in
the instruction encoding.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39016>
2025-12-25 22:57:47 +00:00
Christian Gmeiner 187233339a etnaviv: isa: Print parser error
When a parsing test fails, output the actual error message to aid
debugging. This makes it immediately clear why parsing failed instead
of just showing that the test didn't succeed.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39016>
2025-12-25 22:57:47 +00:00
Samuel Pitoiset b3c983b8dd amd,radv,radeonsi: add a new function to update windowed perf counters
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39065>
2025-12-24 07:20:01 +00:00
Samuel Pitoiset 47366527ce radv: fix capturing performance counters with SPM
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14333
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39065>
2025-12-24 07:20:01 +00:00
Samuel Pitoiset e03461f3bd radv: change the default value of RADV_TRACE_CACHE_COUNTERS on < GFX10
To not print a warning about missing SPM by default on < GFX10.
Also move the function to radv_physical_device.c and make it non-static.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39065>
2025-12-24 07:20:01 +00:00
André 7219411f78 nouveau: fix memory leak by freeing drm version before returning
Fixes: 821f4c8d ("nouveau: import libdrm_nouveau")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Signed-off-by: André Costa <andre_miguel_costa@hotmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39066>
2025-12-23 21:06:39 +01:00
Lorenzo Rossi eced9c8bb7 nak/sm120: Fix panic for CS2R during prepass
Currently the sm120 instruction latency code expects registers to be out
of SSA. This prerequisite is broken with the prepass scheduler.
This commit removes non-SSA-specific code.

Fixes: b55b8da012 ("nak: Add a prepass instruction scheduler")
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Signed-off-by: Lorenzo Rossi <git@rossilorenzo.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39072>
2025-12-23 18:50:30 +00:00
Juan A. Suarez Romero 975fee5697 v3dv/ci: skip tests causing GPU issues
Basically skip tests causing GPU resets.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39075>
2025-12-23 18:26:08 +00:00
Mel Henning 93d0e062a1 nak: Use .file() helper in sm120_instr_latencies
This helper was introduced in b4bac84d3b ("nak: Add a Dst::file()
helper function") which missed updating the sm120 file.

Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39074>
2025-12-23 17:48:08 +00:00
Mel Henning 5f2caf6d63 nak: Take &ShaderModelInfo in instr_sched_common
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39074>
2025-12-23 17:48:08 +00:00
Simon Richter 11325f922d anv, hasvk: Fix reported CPU page size
Memory mappings must be aligned to the smallest page size in use, which may
be 16k or 64k on some systems.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13720
Signed-off-by: Simon Richter <Simon.Richter@hogyros.de>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36801>
2025-12-23 13:22:41 +00:00
Timur Kristóf 450a6189de radv: Initialize transfer queue gang when needed
Initialize gang CS on unsupported transfer operations.

Add a wait when:
- SDMA needs to wait for previous transfer operations on ACE
- ACE needs to wait for previous transfer operations on SDMA

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39057>
2025-12-23 12:14:59 +00:00
Timur Kristóf cc5190829f radv: Declare some gang submit functions in radv private header.
They will be called from the transfer copy functions.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39057>
2025-12-23 12:14:59 +00:00
Timur Kristóf b1938901d0 radv: Use SDMA fence packet when flushing gang semaphores
Add back the SDMA fence packet to radv_flush_gang_semaphore.
This was regressed by 9666bd1245.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39057>
2025-12-23 12:14:59 +00:00
Timur Kristóf d71a05dffa radv: Implement gang semaphores for transfer queues.
We need to use gang semaphores in the following two scenarios:

1. Leader to follower semaphore:
Increment the leader to follower semaphore when the leader wants
to block the follower: a transfer operation on ACE needs to wait
for a previous operation on SDMA.

2. Follower to leader semaphore:
Increment the follower to leader semaphore when the follower wants
to block the leader: a transfer operation on SDMA needs to wait
for a previous operation on ACE.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39057>
2025-12-23 12:14:58 +00:00
Timur Kristóf 4d0975dc83 radv: Update comments for gang semaphores
Change the explanation to use "leader" and "follower" terminology.
Explain better how it is used with GFX/ACE and SDMA/ACE.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39057>
2025-12-23 12:14:58 +00:00
Timur Kristóf 65bf4e7dcd radv: Require gang submit and compute for transfer queues
RADV's transfer queue implementation will use compute for
the transfer operations that aren't supported by the SDMA,
so we'll need gang submissions for that.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39057>
2025-12-23 12:14:58 +00:00
Timur Kristóf f481a5f887 radv: Add function to determine if SDMA supports an image.
The following are not supported by SDMA:
- Sparse images (aka. PRT) on older GPUs
- Multisampled images

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39057>
2025-12-23 12:14:58 +00:00
Timur Kristóf f55771a17d radv: Bypass L2 for gang semaphore BO with SDMA/ACE
When the "gang leader" is SDMA, we need to ensure that the
gang semaphores BO is coherent between SDMA and CP.
To achieve this, we need bypass the L2 cache when either SDMA
or CP are connected to L2.

Suggested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39057>
2025-12-23 12:14:58 +00:00
Linus Karl 7700ba28f5 ethos: fix build on non LP64 architectures
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14310
Signed-off-by: Linus Karl <linus@lotz.li>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38592>
2025-12-23 08:58:26 +00:00
Linus Karl 01cb7d7fd1 rocket: fix build on non LP64 architectures
Cc: mesa-stable
Signed-off-by: Linus Karl <linus@lotz.li>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38592>
2025-12-23 08:58:26 +00:00
Juan A. Suarez Romero 0cab626014 v3d: don't build disk cache access on shader disablement
Don't build shader cache related functions when shader cache is disabled
on compile time.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14512
Backport-to: 25.3
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39064>
2025-12-23 08:42:38 +00:00
Yuxuan Shui e0fbf9a908 wsi/display: Set atomic client cap in Acquire{Drm,Xlib}DisplayEXT as well.
Since we use atomic mode setting now, the wsi->fd we use needs to have
the atomic client cap.

There are several different code paths where wsi can acquire a file
descriptor. For drm masters, the atomic client cap is set in
wsi_display_init_wsi. For leased drm fds, there are AcquireDrmDisplayEXT
and AcquireXlibDisplayEXT.

According to a comment we previously assumed wsi_display_get_connector
is common among all code paths, and that's why the atomic client cap was
set there. But that assumption can be broken based on the particular
order which the application invokes vulkan APIs in.

This commit simply push the drmSetClientCap to all entrypoints where a
drm fd comes through.

Fixes: 513ffea1d3 ("wsi/display: use atomic mode setting")
Signed-off-by: Yuxuan Shui <yshui@codeweavers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38987>
2025-12-23 00:47:26 +00:00
Timur Kristóf 7dbabc6acc ac/nir/lower_taskmesh_io_to_mem: Use AC_TASK_DRAW_ENTRY_BYTES
Replace draw_entry_bytes with AC_TASK_DRAW_ENTRY_BYTES.
This is 16 on all AMD HW that supports task/mesh shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39032>
2025-12-22 15:17:59 +00:00
Timur Kristóf fc57fa4589 radv, radeonsi: Don't pass task ring info to mesh/task payload lowering
The pass now uses the ring descriptors to figure these out.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39032>
2025-12-22 15:17:59 +00:00
Timur Kristóf 4d381c9136 ac/nir/lower_taskmesh_io_to_mem: Don't hardcode payload entry size in shaders
Currently the number of task payload entry size is hardcoded
in shaders as a constant. This isn't a good idea because it
makes the code inflexible, eg. doesn't allow us
to change the number of entries dynamically.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39032>
2025-12-22 15:17:59 +00:00
Timur Kristóf 5348d953aa ac/nir/lower_taskmesh_io_to_mem: Don't hardcode num_entries in shaders
Currently the number of task shader ring entries is hardcoded
in shaders as a constant. This isn't a good idea because it
makes the code inflexible, eg. prevents us from using the same
shader binary accross some chips as well as doesn't allow us
to change the number of entries dynamically.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39032>
2025-12-22 15:17:58 +00:00