Files
mesa/src/intel/compiler
Lionel Landwerlin 67b778445a brw: fix uniform rebuild of sources
If you have something like this :

con 32    %66 = @load_reg (%62) (base=0, legacy_fabs=0, legacy_fneg=0)
con 32    %27 = @resource_intel (%22 (0xdeaddead), %66, %67, %17 (0x0)) (desc_set=2, binding=96, resource_intel=0, resource_block_intel=-1)

Just copying the brw_reg in ssa_values[] is not enough for the
load_reg intrinsic. We need to call get_nir_src() to force some logic
to create the register correct.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b8209d69ff ("intel/fs: Add support for new-style registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30050>
2024-07-18 19:58:46 +00:00
..
2024-02-29 20:47:48 -08:00
2024-05-15 13:13:38 +00:00
2024-05-15 13:13:38 +00:00