nir: introduce discard_is_demote compiler option

This new option indicates that the driver emits the same
code for nir_intrinsic_discard and nir_intrinsic_demote.
Otherwise, it is assumed that discard is implemented as
terminate.

spirv_to_nir uses this option in order to directly emit
nir_demote in case of OpKill.

RADV GFX11:
Totals from 3965 (4.99% of 79439) affected shaders:
MaxWaves: 119418 -> 119424 (+0.01%); split: +0.03%, -0.03%
Instrs: 1608753 -> 1620830 (+0.75%); split: -0.18%, +0.93%
CodeSize: 8759152 -> 8785152 (+0.30%); split: -0.18%, +0.48%
VGPRs: 152292 -> 149232 (-2.01%); split: -2.37%, +0.36%
Latency: 9162314 -> 10033923 (+9.51%); split: -0.46%, +9.97%
InvThroughput: 1491656 -> 1493408 (+0.12%); split: -0.10%, +0.22%
VClause: 21424 -> 21452 (+0.13%); split: -0.31%, +0.44%
SClause: 53598 -> 55871 (+4.24%); split: -2.15%, +6.39%
Copies: 90553 -> 90462 (-0.10%); split: -2.91%, +2.81%
Branches: 16283 -> 16311 (+0.17%)
PreSGPRs: 113993 -> 113254 (-0.65%); split: -1.84%, +1.19%
PreVGPRs: 110951 -> 108914 (-1.84%); split: -2.08%, +0.24%
VALU: 963192 -> 963167 (-0.00%); split: -0.01%, +0.01%
SALU: 87926 -> 90795 (+3.26%); split: -2.92%, +6.18%
VMEM: 25937 -> 25936 (-0.00%)
SMEM: 110012 -> 109799 (-0.19%); split: -0.20%, +0.01%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27617>

src/amd/common/ac_shader_util.c

@@ -93,6 +93,7 @@ void ac_set_nir_options(struct radeon_info *info, bool use_llvm,
    options->lower_fisnormal = true;
    options->support_16bit_alu = info->gfx_level >= GFX8;
    options->vectorize_vec2_16bit = info->has_packed_math_16bit;
+   options->discard_is_demote = true;
 }
 
 bool

src/broadcom/vulkan/v3dv_pipeline.c

@@ -224,6 +224,7 @@ const nir_shader_compiler_options v3dv_nir_options = {
    .force_indirect_unrolling = (nir_var_shader_in | nir_var_function_temp),
    .divergence_analysis_options =
       nir_divergence_multiple_workgroup_per_compute_subgroup,
+   .discard_is_demote = true,
 };
 
 const nir_shader_compiler_options *

src/compiler/nir/nir.h

@@ -4181,6 +4181,12 @@ typedef struct nir_shader_compiler_options {
    /** clip/cull distance and tess level arrays use compact semantics */
    bool compact_arrays;
 
+   /**
+    * Whether discard gets emitted as nir_intrinsic_demote.
+    * Otherwise, nir_intrinsic_terminate is being used.
+    */
+   bool discard_is_demote;
+
    /** Options determining lowering and behavior of inputs and outputs. */
    nir_io_options io_options;
 

src/compiler/spirv/spirv_to_nir.c

@@ -6850,7 +6850,8 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
     * Related glslang issue: https://github.com/KhronosGroup/glslang/issues/2416
     */
    bool dxsc = b->generator_id == vtn_generator_spiregg;
-   b->convert_discard_to_demote = ((dxsc && !b->enabled_capabilities.DemoteToHelperInvocation) ||
+   b->convert_discard_to_demote = (nir_options->discard_is_demote ||
+                                   (dxsc && !b->enabled_capabilities.DemoteToHelperInvocation) ||
                                    (is_glslang(b) && b->source_lang == SpvSourceLanguageHLSL)) &&
                                   b->supported_capabilities.DemoteToHelperInvocation;
 

src/gallium/drivers/zink/zink_compiler.c

@@ -1434,6 +1434,9 @@ zink_screen_init_compiler(struct zink_screen *screen)
        screen->info.driver_props.driverID == VK_DRIVER_ID_AMD_OPEN_SOURCE ||
        screen->info.driver_props.driverID == VK_DRIVER_ID_AMD_PROPRIETARY)
       screen->nir_options.lower_doubles_options = nir_lower_dmod;
+
+   if (screen->info.have_EXT_shader_demote_to_helper_invocation)
+      screen->nir_options.discard_is_demote = true;
 }
 
 const void *

src/intel/compiler/brw_compiler.c

@@ -32,6 +32,7 @@
 const struct nir_shader_compiler_options brw_scalar_nir_options = {
    .avoid_ternary_with_two_constants = true,
    .compact_arrays = true,
+   .discard_is_demote = true,
    .divergence_analysis_options =
       (nir_divergence_single_patch_per_tcs_subgroup |
        nir_divergence_single_patch_per_tes_subgroup |

src/intel/compiler/elk/elk_nir_options.c

@@ -7,6 +7,7 @@
 
 #define COMMON_OPTIONS                                                        \
    .compact_arrays = true,                                                    \
+   .discard_is_demote = true,                                                 \
    .has_uclz = true,                                                          \
    .lower_fdiv = true,                                                        \
    .lower_scmp = true,                                                        \

src/microsoft/ci/spirv2dxil_reference.txt

@@ -603,7 +603,14 @@ Test:SpvParserCFGTest_EmitBody_IfBreak_FromThen_ForwardWithinThen.spvasm:main|Fr
 Test:SpvParserCFGTest_EmitBody_IfBreak_FromThenWithForward_FromElseWithForward_AlsoPremerge.spvasm:main|Fragment: Pass
 Test:SpvParserCFGTest_EmitBody_IfSelection_TrueBranch_LoopBreak.spvasm:main|Fragment: Pass
 Test:SpvParserCFGTest_EmitBody_Kill_InsideIf.spvasm:main|Fragment: Pass
-Test:SpvParserCFGTest_EmitBody_Kill_InsideLoop.spvasm:main|Fragment: Pass
+Test:SpvParserCFGTest_EmitBody_Kill_InsideLoop.spvasm:main|Fragment: Fail
+DXIL: Function: main: error: Loop must have break.
+Validation failed.
+Failed to validate DXIL
+
+
+
+
 Test:SpvParserCFGTest_EmitBody_Kill_TopLevel.spvasm:main|Fragment: Pass
 Test:SpvParserCFGTest_EmitBody_Loop_BodyAlwaysBreaks.spvasm:main|Fragment: Pass
 Test:SpvParserCFGTest_EmitBody_Loop_BodyConditionallyBreaks_FromFalse.spvasm:main|Fragment: Pass

src/microsoft/ci/warp-fails.txt

@@ -0,0 +1,3 @@
+# The CTS expects OpKill to terminate shaders while the spec allows it to be implemented
+# as OpDemoteToHelperInvocation. Wait for pending CTS fix.
+dEQP-VK.graphicsfuzz.while-inside-switch,Fail

src/microsoft/compiler/nir_to_dxil.c

@@ -160,6 +160,7 @@ nir_options = {
    .linker_ignore_precision = true,
    .support_16bit_alu = true,
    .preserve_mediump = true,
+   .discard_is_demote = true,
 };
 
 const nir_shader_compiler_options*

src/nouveau/codegen/nv50_ir_from_nir.cpp

@@ -3506,6 +3506,7 @@ nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dsub : 0) |
       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ddiv : 0)
    );
+   op.discard_is_demote = true;
    return op;
 }
 

src/nouveau/compiler/nak/api.rs

@@ -155,6 +155,7 @@ fn nir_options(dev: &nv_device_info) -> nir_shader_compiler_options {
     op.has_find_msb_rev = true;
     op.has_pack_half_2x16_rtz = true;
     op.has_bfm = dev.sm >= 70;
+    op.discard_is_demote = true;
 
     op.max_unroll_iterations = 32;