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intel/disasm: Fix cache load/store disassembly for URB messages

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28868>
This commit is contained in:
Sagar Ghuge
2024-04-22 21:01:11 -07:00
committed by Marge Bot
parent 925fff229f
commit 69fc7ee622
1 changed files with 4 additions and 0 deletions
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4
src/intel/compiler/brw_disasm.c
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@@ -2254,6 +2254,8 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
case LSC_OP_LOAD:
format(file, ",");
err |= control(file, "cache_load",
devinfo->ver >= 20 ?
xe2_lsc_cache_load :
lsc_cache_load,
lsc_msg_desc_cache_ctrl(devinfo, imm_desc),
&space);
@@ -2261,6 +2263,8 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
default:
format(file, ",");
err |= control(file, "cache_store",
devinfo->ver >= 20 ?
xe2_lsc_cache_store :
lsc_cache_store,
lsc_msg_desc_cache_ctrl(devinfo, imm_desc),
&space);