intel/compiler: Rename the passes and files related to intel_nir.h

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>

src/intel/compiler/brw_fs.cpp

@@ -7652,7 +7652,7 @@ brw_nir_populate_wm_prog_data(nir_shader *shader,
     * pixel shading if we have any intrinsic that will result in a pixel
     * interpolater message at sample.
     */
-   if (brw_nir_pulls_at_sample(shader))
+   if (intel_nir_pulls_at_sample(shader))
       prog_data->coarse_pixel_dispatch = BRW_NEVER;
 
    /* We choose to always enable VMask prior to XeHP, as it would cause

src/intel/compiler/brw_kernel.c

@@ -25,6 +25,7 @@
 #include "brw_nir.h"
 #include "intel_nir.h"
 
+#include "intel_nir.h"
 #include "nir_clc_helpers.h"
 #include "compiler/nir/nir_builder.h"
 #include "compiler/spirv/nir_spirv.h"

src/intel/compiler/brw_nir.c

@@ -928,7 +928,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
     * So when robust image access is enabled, just avoid the workaround.
     */
    if (intel_needs_workaround(devinfo, 1806565034) && !opts->robust_image_access)
-      OPT(brw_nir_clamp_image_1d_2d_array_sizes);
+      OPT(intel_nir_clamp_image_1d_2d_array_sizes);
 
    const nir_lower_tex_options tex_options = {
       .lower_txp = ~0,
@@ -1043,7 +1043,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
     */
    if (nir->info.stage == MESA_SHADER_TESS_CTRL &&
        compiler->use_tcs_multi_patch)
-      OPT(brw_nir_clamp_per_vertex_loads);
+      OPT(intel_nir_clamp_per_vertex_loads);
 
    /* Get rid of split copies */
    brw_nir_optimize(nir, is_scalar, devinfo);
@@ -1510,7 +1510,7 @@ brw_vectorize_lower_mem_access(nir_shader *nir,
           *   - reduced register pressure
           */
          nir_divergence_analysis(nir);
-         if (OPT(brw_nir_blockify_uniform_loads, compiler->devinfo))
+         if (OPT(intel_nir_blockify_uniform_loads, compiler->devinfo))
             OPT(nir_opt_load_store_vectorize, &options);
          OPT(nir_opt_remove_phis);
       }
@@ -1568,7 +1568,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
 
    UNUSED bool progress; /* Written by OPT */
 
-   OPT(brw_nir_lower_sparse_intrinsics);
+   OPT(intel_nir_lower_sparse_intrinsics);
 
    OPT(nir_lower_bit_size, lower_bit_size_callback, (void *)compiler);
 
@@ -1589,7 +1589,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
    }
 
    if (gl_shader_stage_can_set_fragment_shading_rate(nir->info.stage))
-      NIR_PASS(_, nir, brw_nir_lower_shading_rate_output);
+      NIR_PASS(_, nir, intel_nir_lower_shading_rate_output);
 
    brw_nir_optimize(nir, is_scalar, devinfo);
 
@@ -1618,12 +1618,12 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
        *    vec1  ssa_1 = fneg ssa_0.x
        *    vec1  ssa_2 = ffma ssa_1, ...
        */
-      if (OPT(brw_nir_opt_peephole_ffma))
+      if (OPT(intel_nir_opt_peephole_ffma))
          OPT(nir_opt_shrink_vectors);
    }
 
    if (is_scalar)
-      OPT(brw_nir_opt_peephole_imul32x16);
+      OPT(intel_nir_opt_peephole_imul32x16);
 
    if (OPT(nir_opt_comparison_pre)) {
       OPT(nir_copy_prop);
@@ -1668,7 +1668,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
       }
    }
 
-   OPT(brw_nir_lower_conversions);
+   OPT(intel_nir_lower_conversions);
 
    if (is_scalar)
       OPT(nir_lower_alu_to_scalar, NULL, NULL);
@@ -1724,7 +1724,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
          NIR_PASS_V(nir, nir_divergence_analysis);
       }
 
-      OPT(brw_nir_lower_non_uniform_barycentric_at_sample);
+      OPT(intel_nir_lower_non_uniform_barycentric_at_sample);
    }
 
    /* Clean up LCSSA phis */
@@ -1896,10 +1896,10 @@ brw_nir_apply_key(nir_shader *nir,
 
    OPT(brw_nir_apply_sampler_key, compiler, &key->tex);
 
-   const struct brw_nir_lower_texture_opts tex_opts = {
+   const struct intel_nir_lower_texture_opts tex_opts = {
       .combined_lod_and_array_index = compiler->devinfo->ver >= 20,
    };
-   OPT(brw_nir_lower_texture, &tex_opts);
+   OPT(intel_nir_lower_texture, &tex_opts);
 
    const nir_lower_subgroups_options subgroups_options = {
       .subgroup_size = get_subgroup_size(&nir->info, max_subgroup_size),

src/intel/compiler/brw_nir_rt.c

@@ -21,6 +21,7 @@
  * IN THE SOFTWARE.
  */
 
+#include "intel_nir.h"
 #include "brw_nir_rt.h"
 #include "brw_nir_rt_builder.h"
 #include "intel_nir.h"

src/intel/compiler/brw_vec4_tcs.cpp

@@ -384,9 +384,9 @@ brw_compile_tcs(const struct brw_compiler *compiler,
    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
                              key->_tes_primitive_mode);
    if (key->quads_workaround)
-      brw_nir_apply_tcs_quads_workaround(nir);
+      intel_nir_apply_tcs_quads_workaround(nir);
    if (key->input_vertices > 0)
-      brw_nir_lower_patch_vertices_in(nir, key->input_vertices);
+      intel_nir_lower_patch_vertices_in(nir, key->input_vertices);
 
    brw_postprocess_nir(nir, compiler, debug_enabled,
                        key->base.robust_flags);

src/intel/compiler/intel_nir.c

@@ -6,7 +6,7 @@
 #include "intel_nir.h"
 
 bool
-brw_nir_pulls_at_sample(nir_shader *shader)
+intel_nir_pulls_at_sample(nir_shader *shader)
 {
    nir_foreach_function_impl(impl, shader) {
       nir_foreach_block(block, impl) {

src/intel/compiler/intel_nir.h

@@ -14,27 +14,30 @@ extern "C" {
 
 struct intel_device_info;
 
-bool brw_nir_lower_conversions(nir_shader *nir);
-bool brw_nir_lower_shading_rate_output(nir_shader *nir);
-bool brw_nir_lower_sparse_intrinsics(nir_shader *nir);
-bool brw_nir_lower_non_uniform_resource_intel(nir_shader *shader);
-bool brw_nir_cleanup_resource_intel(nir_shader *shader);
-bool brw_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader);
-void brw_nir_apply_tcs_quads_workaround(nir_shader *nir);
-bool brw_nir_lower_non_uniform_barycentric_at_sample(nir_shader *nir);
-bool brw_nir_opt_peephole_ffma(nir_shader *shader);
-bool brw_nir_opt_peephole_imul32x16(nir_shader *shader);
-bool brw_nir_clamp_per_vertex_loads(nir_shader *shader);
-bool brw_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices);
-bool brw_nir_blockify_uniform_loads(nir_shader *shader,
-                                    const struct intel_device_info *devinfo);
-bool brw_nir_pulls_at_sample(nir_shader *shader);
+void intel_nir_apply_tcs_quads_workaround(nir_shader *nir);
+bool intel_nir_blockify_uniform_loads(nir_shader *shader,
+                                      const struct intel_device_info *devinfo);
+bool intel_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader);
+bool intel_nir_clamp_per_vertex_loads(nir_shader *shader);
+bool intel_nir_cleanup_resource_intel(nir_shader *shader);
 
-struct brw_nir_lower_texture_opts {
+bool intel_nir_lower_conversions(nir_shader *nir);
+bool intel_nir_lower_non_uniform_barycentric_at_sample(nir_shader *nir);
+bool intel_nir_lower_non_uniform_resource_intel(nir_shader *shader);
+bool intel_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices);
+bool intel_nir_lower_shading_rate_output(nir_shader *nir);
+bool intel_nir_lower_sparse_intrinsics(nir_shader *nir);
+
+struct intel_nir_lower_texture_opts {
    bool combined_lod_and_array_index;
 };
-bool brw_nir_lower_texture(nir_shader *nir,
-                           const struct brw_nir_lower_texture_opts *opts);
+bool intel_nir_lower_texture(nir_shader *nir,
+                             const struct intel_nir_lower_texture_opts *opts);
+
+bool intel_nir_opt_peephole_ffma(nir_shader *shader);
+bool intel_nir_opt_peephole_imul32x16(nir_shader *shader);
+
+bool intel_nir_pulls_at_sample(nir_shader *shader);
 
 #ifdef __cplusplus
 }

src/intel/compiler/intel_nir_blockify_uniform_loads.c

@@ -27,9 +27,9 @@
 #include "nir_builder.h"
 
 static bool
-brw_nir_blockify_uniform_loads_instr(nir_builder *b,
-                                     nir_instr *instr,
-                                     void *cb_data)
+intel_nir_blockify_uniform_loads_instr(nir_builder *b,
+                                       nir_instr *instr,
+                                       void *cb_data)
 {
    if (instr->type != nir_instr_type_intrinsic)
       return false;
@@ -104,11 +104,11 @@ brw_nir_blockify_uniform_loads_instr(nir_builder *b,
 }
 
 bool
-brw_nir_blockify_uniform_loads(nir_shader *shader,
-                               const struct intel_device_info *devinfo)
+intel_nir_blockify_uniform_loads(nir_shader *shader,
+                                 const struct intel_device_info *devinfo)
 {
    return nir_shader_instructions_pass(shader,
-                                       brw_nir_blockify_uniform_loads_instr,
+                                       intel_nir_blockify_uniform_loads_instr,
                                        nir_metadata_block_index |
                                        nir_metadata_dominance |
                                        nir_metadata_live_defs,

src/intel/compiler/intel_nir_clamp_image_1d_2d_array_sizes.c

@@ -37,9 +37,9 @@
  */
 
 static bool
-brw_nir_clamp_image_1d_2d_array_sizes_instr(nir_builder *b,
-                                            nir_instr *instr,
-                                            UNUSED void *cb_data)
+intel_nir_clamp_image_1d_2d_array_sizes_instr(nir_builder *b,
+                                              nir_instr *instr,
+                                              UNUSED void *cb_data)
 {
    nir_def *image_size = NULL;
 
@@ -134,10 +134,10 @@ brw_nir_clamp_image_1d_2d_array_sizes_instr(nir_builder *b,
 }
 
 bool
-brw_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader)
+intel_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader)
 {
    return nir_shader_instructions_pass(shader,
-                                       brw_nir_clamp_image_1d_2d_array_sizes_instr,
+                                       intel_nir_clamp_image_1d_2d_array_sizes_instr,
                                        nir_metadata_block_index |
                                        nir_metadata_dominance,
                                        NULL);

src/intel/compiler/intel_nir_clamp_per_vertex_loads.c

@@ -68,7 +68,7 @@ clamp_per_vertex_loads_instr(nir_builder *b, nir_intrinsic_instr *intrin,
 }
 
 bool
-brw_nir_clamp_per_vertex_loads(nir_shader *shader)
+intel_nir_clamp_per_vertex_loads(nir_shader *shader)
 {
    void *mem_ctx = ralloc_context(NULL);
 
@@ -99,7 +99,7 @@ lower_patch_vertices_instr(nir_builder *b, nir_intrinsic_instr *intrin,
 }
 
 bool
-brw_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices)
+intel_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices)
 {
    return nir_shader_intrinsics_pass(shader, lower_patch_vertices_instr,
                                        nir_metadata_block_index |

src/intel/compiler/intel_nir_lower_conversions.c

@@ -106,7 +106,7 @@ lower_instr(nir_builder *b, nir_instr *instr, UNUSED void *cb_data)
 }
 
 bool
-brw_nir_lower_conversions(nir_shader *shader)
+intel_nir_lower_conversions(nir_shader *shader)
 {
    return nir_shader_instructions_pass(shader, lower_instr,
                                        nir_metadata_block_index |

src/intel/compiler/intel_nir_lower_non_uniform_barycentric_at_sample.c

@@ -33,9 +33,9 @@
 #include "compiler/nir/nir_builder.h"
 
 static bool
-brw_nir_lower_non_uniform_barycentric_at_sample_instr(nir_builder *b,
-                                                      nir_instr *instr,
-                                                      void *cb_data)
+intel_nir_lower_non_uniform_barycentric_at_sample_instr(nir_builder *b,
+                                                        nir_instr *instr,
+                                                        void *cb_data)
 {
    if (instr->type != nir_instr_type_intrinsic)
       return false;
@@ -70,11 +70,11 @@ brw_nir_lower_non_uniform_barycentric_at_sample_instr(nir_builder *b,
 }
 
 bool
-brw_nir_lower_non_uniform_barycentric_at_sample(nir_shader *nir)
+intel_nir_lower_non_uniform_barycentric_at_sample(nir_shader *nir)
 {
    return nir_shader_instructions_pass(
       nir,
-      brw_nir_lower_non_uniform_barycentric_at_sample_instr,
+      intel_nir_lower_non_uniform_barycentric_at_sample_instr,
       nir_metadata_none,
       NULL);
 }

src/intel/compiler/intel_nir_lower_non_uniform_resource_intel.c

@@ -76,9 +76,9 @@ find_resource_intel(struct util_dynarray *inst_array,
 }
 
 static bool
-brw_nir_lower_non_uniform_intrinsic(nir_builder *b,
-                                    nir_intrinsic_instr *intrin,
-                                    struct util_dynarray *inst_array)
+intel_nir_lower_non_uniform_intrinsic(nir_builder *b,
+                                      nir_intrinsic_instr *intrin,
+                                      struct util_dynarray *inst_array)
 {
    unsigned source;
    switch (intrin->intrinsic) {
@@ -138,9 +138,9 @@ brw_nir_lower_non_uniform_intrinsic(nir_builder *b,
 }
 
 static bool
-brw_nir_lower_non_uniform_tex(nir_builder *b,
-                              nir_tex_instr *tex,
-                              struct util_dynarray *inst_array)
+intel_nir_lower_non_uniform_tex(nir_builder *b,
+                                nir_tex_instr *tex,
+                                struct util_dynarray *inst_array)
 {
    b->cursor = nir_before_instr(&tex->instr);
 
@@ -175,22 +175,22 @@ brw_nir_lower_non_uniform_tex(nir_builder *b,
 }
 
 static bool
-brw_nir_lower_non_uniform_instr(nir_builder *b,
-                                nir_instr *instr,
-                                void *cb_data)
+intel_nir_lower_non_uniform_instr(nir_builder *b,
+                                  nir_instr *instr,
+                                  void *cb_data)
 {
    struct util_dynarray *inst_array = cb_data;
 
    switch (instr->type) {
    case nir_instr_type_intrinsic:
-      return brw_nir_lower_non_uniform_intrinsic(b,
-                                                 nir_instr_as_intrinsic(instr),
-                                                 inst_array);
+      return intel_nir_lower_non_uniform_intrinsic(b,
+                                                   nir_instr_as_intrinsic(instr),
+                                                   inst_array);
 
    case nir_instr_type_tex:
-      return brw_nir_lower_non_uniform_tex(b,
-                                           nir_instr_as_tex(instr),
-                                           inst_array);
+      return intel_nir_lower_non_uniform_tex(b,
+                                             nir_instr_as_tex(instr),
+                                             inst_array);
 
    default:
       return false;
@@ -216,7 +216,7 @@ brw_nir_lower_non_uniform_instr(nir_builder *b,
  * table or bindless access, etc...).
  */
 bool
-brw_nir_lower_non_uniform_resource_intel(nir_shader *shader)
+intel_nir_lower_non_uniform_resource_intel(nir_shader *shader)
 {
    void *mem_ctx = ralloc_context(NULL);
 
@@ -224,7 +224,7 @@ brw_nir_lower_non_uniform_resource_intel(nir_shader *shader)
    util_dynarray_init(&inst_array, mem_ctx);
 
    bool ret = nir_shader_instructions_pass(shader,
-                                           brw_nir_lower_non_uniform_instr,
+                                           intel_nir_lower_non_uniform_instr,
                                            nir_metadata_block_index |
                                            nir_metadata_dominance,
                                            &inst_array);
@@ -279,9 +279,9 @@ skip_resource_intel_cleanup(nir_instr *instr)
 }
 
 static bool
-brw_nir_cleanup_resource_intel_instr(nir_builder *b,
-                                     nir_intrinsic_instr *intrin,
-                                     void *cb_data)
+intel_nir_cleanup_resource_intel_instr(nir_builder *b,
+                                       nir_intrinsic_instr *intrin,
+                                       void *cb_data)
 {
    if (intrin->intrinsic != nir_intrinsic_resource_intel)
       return false;
@@ -300,18 +300,18 @@ brw_nir_cleanup_resource_intel_instr(nir_builder *b,
 
 /** This pass removes unnecessary resource_intel intrinsics
  *
- * This pass must not be run before brw_nir_lower_non_uniform_resource_intel.
+ * This pass must not be run before intel_nir_lower_non_uniform_resource_intel.
  */
 bool
-brw_nir_cleanup_resource_intel(nir_shader *shader)
+intel_nir_cleanup_resource_intel(nir_shader *shader)
 {
    void *mem_ctx = ralloc_context(NULL);
 
    bool ret = nir_shader_intrinsics_pass(shader,
-                                           brw_nir_cleanup_resource_intel_instr,
-                                           nir_metadata_block_index |
-                                           nir_metadata_dominance,
-                                           NULL);
+                                         intel_nir_cleanup_resource_intel_instr,
+                                         nir_metadata_block_index |
+                                         nir_metadata_dominance,
+                                         NULL);
 
    ralloc_free(mem_ctx);
 

src/intel/compiler/intel_nir_lower_shading_rate_output.c

@@ -100,7 +100,7 @@ lower_shading_rate_output_instr(nir_builder *b, nir_intrinsic_instr *intrin,
 }
 
 bool
-brw_nir_lower_shading_rate_output(nir_shader *nir)
+intel_nir_lower_shading_rate_output(nir_shader *nir)
 {
    return nir_shader_intrinsics_pass(nir, lower_shading_rate_output_instr,
                                        nir_metadata_block_index |

src/intel/compiler/intel_nir_lower_sparse.c

@@ -238,7 +238,7 @@ lower_sparse_intrinsics(nir_builder *b, nir_instr *instr, void *cb_data)
 }
 
 bool
-brw_nir_lower_sparse_intrinsics(nir_shader *nir)
+intel_nir_lower_sparse_intrinsics(nir_shader *nir)
 {
    return nir_shader_instructions_pass(nir, lower_sparse_intrinsics,
                                        nir_metadata_block_index |

src/intel/compiler/intel_nir_lower_texture.c

@@ -97,12 +97,12 @@ pack_lod_and_array_index(nir_builder *b, nir_tex_instr *tex)
 }
 
 static bool
-brw_nir_lower_texture_instr(nir_builder *b, nir_instr *instr, void *cb_data)
+intel_nir_lower_texture_instr(nir_builder *b, nir_instr *instr, void *cb_data)
 {
    if (instr->type != nir_instr_type_tex)
       return false;
 
-   const struct brw_nir_lower_texture_opts *opts = cb_data;
+   const struct intel_nir_lower_texture_opts *opts = cb_data;
    nir_tex_instr *tex = nir_instr_as_tex(instr);
 
    switch (tex->op) {
@@ -123,11 +123,11 @@ brw_nir_lower_texture_instr(nir_builder *b, nir_instr *instr, void *cb_data)
 }
 
 bool
-brw_nir_lower_texture(nir_shader *shader,
-                      const struct brw_nir_lower_texture_opts *opts)
+intel_nir_lower_texture(nir_shader *shader,
+                        const struct intel_nir_lower_texture_opts *opts)
 {
    return nir_shader_instructions_pass(shader,
-                                       brw_nir_lower_texture_instr,
+                                       intel_nir_lower_texture_instr,
                                        nir_metadata_none,
                                        (void *)opts);
 }

src/intel/compiler/intel_nir_opt_peephole_ffma.c

@@ -154,9 +154,9 @@ any_alu_src_is_a_constant(nir_alu_src srcs[])
 }
 
 static bool
-brw_nir_opt_peephole_ffma_instr(nir_builder *b,
-                                nir_instr *instr,
-                                UNUSED void *cb_data)
+intel_nir_opt_peephole_ffma_instr(nir_builder *b,
+                                  nir_instr *instr,
+                                  UNUSED void *cb_data)
 {
    if (instr->type != nir_instr_type_alu)
       return false;
@@ -244,9 +244,9 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b,
 }
 
 bool
-brw_nir_opt_peephole_ffma(nir_shader *shader)
+intel_nir_opt_peephole_ffma(nir_shader *shader)
 {
-   return nir_shader_instructions_pass(shader, brw_nir_opt_peephole_ffma_instr,
+   return nir_shader_instructions_pass(shader, intel_nir_opt_peephole_ffma_instr,
                                        nir_metadata_block_index |
                                        nir_metadata_dominance,
                                        NULL);

src/intel/compiler/intel_nir_opt_peephole_imul32x16.c

@@ -184,9 +184,9 @@ signed_integer_range_analysis(nir_shader *shader, struct hash_table *range_ht,
 }
 
 static bool
-brw_nir_opt_peephole_imul32x16_instr(nir_builder *b,
-                                     nir_instr *instr,
-                                     void *cb_data)
+intel_nir_opt_peephole_imul32x16_instr(nir_builder *b,
+                                       nir_instr *instr,
+                                       void *cb_data)
 {
    struct pass_data *d = (struct pass_data *) cb_data;
    struct hash_table *range_ht = d->range_ht;
@@ -300,14 +300,14 @@ brw_nir_opt_peephole_imul32x16_instr(nir_builder *b,
 }
 
 bool
-brw_nir_opt_peephole_imul32x16(nir_shader *shader)
+intel_nir_opt_peephole_imul32x16(nir_shader *shader)
 {
    struct pass_data cb_data;
 
    cb_data.range_ht = _mesa_pointer_hash_table_create(NULL);
 
    bool progress = nir_shader_instructions_pass(shader,
-                                                brw_nir_opt_peephole_imul32x16_instr,
+                                                intel_nir_opt_peephole_imul32x16_instr,
                                                 nir_metadata_block_index |
                                                 nir_metadata_dominance,
                                                 &cb_data);

src/intel/compiler/intel_nir_tcs_workarounds.c

@@ -105,7 +105,7 @@ emit_quads_workaround(nir_builder *b, nir_block *block)
 }
 
 void
-brw_nir_apply_tcs_quads_workaround(nir_shader *nir)
+intel_nir_apply_tcs_quads_workaround(nir_shader *nir)
 {
    assert(nir->info.stage == MESA_SHADER_TESS_CTRL);
 

src/intel/compiler/meson.build

@@ -22,18 +22,18 @@ intel_nir_files = files(
   'intel_nir.h',
   'intel_nir.c',
 
-  'brw_nir_blockify_uniform_loads.c',
-  'brw_nir_clamp_image_1d_2d_array_sizes.c',
-  'brw_nir_clamp_per_vertex_loads.c',
-  'brw_nir_lower_conversions.c',
-  'brw_nir_lower_non_uniform_barycentric_at_sample.c',
-  'brw_nir_lower_non_uniform_resource_intel.c',
-  'brw_nir_lower_shading_rate_output.c',
-  'brw_nir_lower_sparse.c',
-  'brw_nir_lower_texture.c',
-  'brw_nir_opt_peephole_ffma.c',
-  'brw_nir_opt_peephole_imul32x16.c',
-  'brw_nir_tcs_workarounds.c',
+  'intel_nir_blockify_uniform_loads.c',
+  'intel_nir_clamp_image_1d_2d_array_sizes.c',
+  'intel_nir_clamp_per_vertex_loads.c',
+  'intel_nir_lower_conversions.c',
+  'intel_nir_lower_non_uniform_barycentric_at_sample.c',
+  'intel_nir_lower_non_uniform_resource_intel.c',
+  'intel_nir_lower_shading_rate_output.c',
+  'intel_nir_lower_sparse.c',
+  'intel_nir_lower_texture.c',
+  'intel_nir_opt_peephole_ffma.c',
+  'intel_nir_opt_peephole_imul32x16.c',
+  'intel_nir_tcs_workarounds.c',
 )
 
 libintel_compiler_files = files(

src/intel/vulkan/anv_internal_kernels.c

@@ -23,6 +23,7 @@
 
 #include "anv_private.h"
 
+#include "compiler/intel_nir.h"
 #include "compiler/brw_compiler.h"
 #include "compiler/brw_nir.h"
 #include "compiler/nir/nir.h"

src/intel/vulkan/anv_pipeline.c

@@ -1126,8 +1126,8 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
                   .callback = NULL,
                });
 
-      NIR_PASS(_, nir, brw_nir_lower_non_uniform_resource_intel);
-      NIR_PASS(_, nir, brw_nir_cleanup_resource_intel);
+      NIR_PASS(_, nir, intel_nir_lower_non_uniform_resource_intel);
+      NIR_PASS(_, nir, intel_nir_cleanup_resource_intel);
       NIR_PASS(_, nir, nir_opt_dce);
    }