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Author SHA1 Message Date
Pavel Ondračka f56f277ba0 r300: set register file to none if swizzles are constant only 
In constant folding when converting multiply by zero to mov.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21141>
 2023-02-06 20:31:56 +00:00
Kai Wasserbäch 1d5d07e565 fix: gallivm: limit usage of LLVMContextSetOpaquePointers() to LLVM 15 
LLVMContextSetOpaquePointers() was a temporary workaround offered to
allow transitioning to opaque pointers. Mesa is ready for this now with
recent versions of LLVM (16+). Therefore we limit the workaround of
using LLVMContextSetOpaquePointers() to LLVM 15 now, that this C
interface was removed in LLVM 17.

Reference: https://github.com/llvm/llvm-project/commit/1270879376025457e266572c7cccc51eb5de9276
Suggested-by: Dave Airlie <airlied@redhat.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8183
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21124>
 2023-02-06 19:50:35 +00:00
Konstantin Seurer 569517d7ad radv: Use common ycbcr conversion lowering 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20731>
 2023-02-06 18:36:29 +00:00
Konstantin Seurer 9104dafb6f vulkan,nir: Refactor ycbcr conversion state into a struct 
This will be useful for RADV since it hashes the state.

v3dv changes:
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20731>
 2023-02-06 18:36:29 +00:00
Konstantin Seurer dae893cb96 radv: Remove radv_indirect_unaligned_dispatch 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21071>
 2023-02-06 17:50:53 +00:00
Konstantin Seurer b9d7306edc radv: Use an ordered dispatch for BVH encoding 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21071>
 2023-02-06 17:50:53 +00:00
Konstantin Seurer 22a028ea99 radv: Implement ordered compute dispatches 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21071>
 2023-02-06 17:50:53 +00:00
Konstantin Seurer 77b0a4c025 radv: Make radv_compute_dispatch non-static 
To avoid adding yet another radv_*_dispatch helper.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21071>
 2023-02-06 17:50:53 +00:00
Guilherme Gallo 26754f658e Revert "ci: disable Collabora's LAVA lab for maintance" 
This reverts commit 60d7e15a7e.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20903>
 2023-02-06 17:22:11 +00:00
Guilherme Gallo 95b5cc3a53 radeonsi/ci: Skip slow traces on raven 
Two traces timed out during Collabora's LAVA farm re-enablement.
Possibly, some commit made them slower during farm downtime.

- https://gitlab.freedesktop.org/mesa/mesa/-/jobs/35934124

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20903>
 2023-02-06 17:22:11 +00:00
Guilherme Gallo 53cc509288 radeonsi/ci: Update stoney test expectations 
Some jobs failed during the re-enablement of Collabora's LAVA farm.

The trace job radeonsi-stoney-traces:amd64 produced some traces with
almost unnoticeable lighting spread difference, so I updated all the
traces.

Now the test spec@ext_texture_lod_bias@lodbias is failing after running
a couple of times.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20903>
 2023-02-06 17:22:11 +00:00
Jonathan Gray f15f08c3de intel/dev: Add another EHL pci id 
described as "32 Execution Unit (EU) Super SKU" in:
Intel Atom x6000E Series, and Intel Pentium and Celeron N and
J Series Processors for IoT Applications
Datasheet, Volume 1
Document Number: 636112-1.6

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21129>
 2023-02-06 16:48:39 +00:00
Jonathan Gray a23e04b673 intel/dev: remove invalid EHL pci id 
removed in linux
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21129>
 2023-02-06 16:48:39 +00:00
Mike Blumenkrantz 89cf0a3bdc zink: fix max acquired image count 
according to spec, the maximum number of acquired images can be calculated with

swapchain_size - VkSurfaceCapabilitiesKHR::minImageCount + 1

the previous calculation was both wrong and occurring in the wrong place,
so this corrects both issues

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21095>
 2023-02-06 16:35:48 +00:00
SoroushIMG 22e91af1a7 zink: clear null image surfaces to 0 
GL Spec says that imageLoad from incomplete images must return 0.
This is not really spec compliant as for proper behavior nullDescriptor
and robustImageAccess2 is needed.
A workaround for lack of either of these requires a shader variant.
Clearing the null surface and hoping the app doesn't write to the image
is closer to spec, while avoiding a shader recompile.

KHR-GL46.shader_image_load_store.incomplete_textures tests this.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21135>
 2023-02-06 15:55:57 +00:00
Samuel Pitoiset 2fe3cef367 radv: do not insert fast-linked libraries to the shaders cache 
Similar to fast-linked pipelines that aren't added to the cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21133>
 2023-02-06 15:01:30 +00:00
SoroushIMG 104040b5c7 zink: fix leak when rebinding same image surface 
simple way to reproduce this is to run these 4 together:
KHR-GL46.gpu_shader5.images_array_indexing
KHR-GL46.shader_image_load_store.advanced-allMips
KHR-GL46.shader_image_load_store.advanced-sso-simple
KHR-GL46.shader_image_load_store.incomplete_textures

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21134>
 2023-02-06 14:47:47 +00:00
SoroushIMG 4c647c9e25 zink: only save frag const buffers when used by blit 
fixes upload manager constant buffer leak.
zink only needs to save the const buffer for stencil fallback blits.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21134>
 2023-02-06 14:47:47 +00:00
Rhys Perry c68f9ed020 radv/llvm: use the ring_offsets shader arg 
Besides being nicer, this also fixes load_sample_positions_amd with LLVM.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>
 2023-02-06 14:25:16 +00:00
Rhys Perry be6f30a0db ac/llvm: let ring_offsets be accessed like a normal arg 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>
 2023-02-06 14:25:16 +00:00
Rhys Perry 24618721d3 ac: move ring_offsets to ac_shader_args 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>
 2023-02-06 14:25:15 +00:00
Rhys Perry 10a5035c83 radv: set state.vbo_misaligned_mask_invalid in radv_bind_vs_input_state 
Found by inspection. Something probably hangs because of this, but I don't
know what.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: c199a5160a ("radv: bind the VS input state for prologs created with GPL")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20913>
 2023-02-06 14:05:13 +00:00
Luigi Santivetti 21f0fc65b2 pvr: add padding bytes when allocating buffer memory 
We need to pad VkBuffers to ensure we don't read beyond a page boundary.

An alternative to this approach would be to allocate an additional virtual
page when binding memory to the buffer, and to map this to the first
physical address, so both the first and last virtual page point to the same
physical location. This would be less expensive in terms of memory usage,
but more complex and invasive, hence the simpler approach has been taken
for now.

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21101>
 2023-02-06 11:18:38 +00:00
Karmjit Mahil 4e75e1bfec pvr: Set SPMSCRATCHBUFFER flag. 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
 2023-02-06 10:47:38 +00:00
Karmjit Mahil ad8c0878b4 pvr: Update comment about ZS and MSAA buffers for pvrsrvkm submission. 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
 2023-02-06 10:47:38 +00:00
Karmjit Mahil 3457f8083a pvr: Acquire scratch buffer on framebuffer creation. 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
 2023-02-06 10:47:38 +00:00
Karmjit Mahil ad9c61c292 pvr: Add SPM scratch buffer infrastructure. 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
 2023-02-06 10:47:38 +00:00
Lionel Landwerlin e37f458207 intel/ds: track end of pipe bits 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Lionel Landwerlin a242500eb4 anv: rename a few internal functions to highlight gfx use 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Lionel Landwerlin 6a23b18730 anv: rename RT pipeline function helper 
Making it clear this is intended for RT pipelines only.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Lionel Landwerlin fd7debc8bb intel/fs: make alpha_to_coverage a tristate 
That way in some cases we can do this dynamically.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Jason Ekstrand f3969e2413 intel/fs: Rework dynamic coarse handling 
Use 2 flags for PI & RT messages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Jason Ekstrand 964b878986 intel/fs: Break out yet another FB write helper 
This new helper, do_emit_fb_writes() does the actual walk over all the
render targets to emit each of the different FB writes.  We want this in
a helper because we're about to go a bit crazy with coarse.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Jason Ekstrand 9c658b1fc8 intel/fs/validate: Assert SEND [extended] descriptors are uniform 
This is required by code-gen since it generates a 1-wide OR and it'll
blow up if the register width > 1.  It's also way better than the "your
register is the wrong size" assert you get from the more generic
validation check.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Jason Ekstrand 949b42c4dc intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-state 
This allows us to communicate to the back-end that we don't actually
know if the framebuffer is multisampled or not.  No drivers set anything
but ALWAYS/NEVER and we still have a few ALWAYS/NEVER assumptions but
those should be asserted.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Jason Ekstrand 5644011f06 intel/compiler: Convert wm_prog_key::persample_interp to a tri-state 
This allows for the possibility that we may not know at compile time if
sample shading is enabled through the API.  While we're here, also
document exactly what this bit means so we don't confuse ourselves.

v2: Fixup coarse pixel values (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Jason Ekstrand d8dfd153c5 intel/fs: Make per-sample and coarse dispatch tri-state 
Whenever one of them is BRW_SOMETIMES, we depend on dynamic flag pushed
in as a push constant.  In this case, we have to often have to do the
calculation both ways and SEL the result.  It's a bit more code but
decouples MSAA from the shader key.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:18 +00:00
Jason Ekstrand 43ca7f4178 intel/compiler: Convert brw_wm_aa_enable to brw_sometimes 
There are other cases where we want a tri-state logic like this.  May as
well have one enum for all the cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:17 +00:00
Jason Ekstrand 5d1c538449 intel/fs: Return early in a couple builtin setup helpers 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:17 +00:00
Jason Ekstrand 714a291673 intel/compiler: Use SHADER_OPCODE_SEND for PI messages 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:17 +00:00
Jason Ekstrand 9c62e0c77d nir: Remove nir_lower_io_force_sample_interpolation 
It's no longer used.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:17 +00:00
Jason Ekstrand d25e5310bc intel/nir: Lower barycentrics to per-sample in a dedicated pass 
This is more similar to what we do for single-sample and it should be
more clear going forward once our lowering gets more complex.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:17 +00:00
Jason Ekstrand 991d546102 intel/compiler: Document wm_prog_key::persample_interp 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
 2023-02-06 09:12:17 +00:00
Marek Olšák 71a6b53192 amd: don't hardcode real VGPR allocation granularity on gfx10.3 and gfx11 
That's how it really works.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
 2023-02-05 23:23:58 -05:00
Marek Olšák e673bb4ae4 amd,util: fix how lod bias is converted to fixed-point 
according to internal docs

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
 2023-02-05 23:23:45 -05:00
Marek Olšák fb5d31c3dd amd/surface: clean up is_dcc_supported_by_L2 
no functional change, though this removes "<=" for navi10, which was
never true in the "<" case

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
 2023-02-05 23:23:45 -05:00
Marek Olšák 70d228188a radeonsi: clean up si_set_mutable_tex_desc_fields 
- sink code into existing branches
- remove unnecessary clearing of fields
- no functional change

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
 2023-02-05 23:23:45 -05:00
Marek Olšák 4f246f27b1 amd: define new SET_*_REG_PAIRS packets 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
 2023-02-05 23:23:45 -05:00
Marek Olšák 97f30fc65f radeonsi/gfx11: don't add alpha to mrt0 format for A2C if exporting via mrtz 
If alpha-to-coverage is exported via mrtz, don't upgrade the mrt0 format
to one with an alpha channel.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
 2023-02-05 23:23:45 -05:00
Marek Olšák 0f81224e70 radeonsi/gfx11: don't add mrt0 export for alpha-to-coverage if mrtz is present 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
 2023-02-05 23:23:45 -05:00