Commit Graph

104180 Commits

Author SHA1 Message Date
Timothy Arceri f0a8accb0d radv: add Doom workaround
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-16 07:53:38 +10:00
Sergii Romantsov efb28aa970 i965: Emitting 3DSTATE_SO_BUFFER of 0-size.
Avoided filling of whole structure and bo-allocation if
size of surface is 0.

Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
2018-08-15 13:15:28 -07:00
Erik Faye-Lund 98b3b6367a virgl: report actual max-texture sizes
Instead of doing conservative guesses, we should report the max levels
based on the max sizes we get from GL on the host.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>
2018-08-15 18:48:16 +02:00
Erik Faye-Lund 825aaeae39 virgl: do not use SP_MAX_TEXTURE_*_LEVELS defines
These macro-names are also used for softpipe, so let's avoid confusion
by avoiding them. Besides, they are just used in one place in virgl, so
let's just inline them into the place they are used instead.

While we're at it, fixup an error in the comment for the 3D version.
Mesa subtracts computes max-size by doing by 2^(n-1), which means this
should be 256 cubed, not 512 cubed. The other comments are correct.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>
2018-08-15 18:48:08 +02:00
Dylan Baker ef7ae84daf docs: Add news item for 18.1.6 2018-08-15 09:09:59 -07:00
Samuel Pitoiset 71d5b2fbf8 radv: disable the auto-waitcnt-before-barrier LLVM option
This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.

Though, apparently there is a problem with LDS accesses that
causes rendering issues with FFXV and DXVK. Disable this
optimization for now (RadeonSI still uses it).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-15 16:21:50 +02:00
Samuel Pitoiset 85113c4d05 radv: fix memory leaks in radv_load_meta_pipeline()
Reported by Coverity.

Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-15 16:20:58 +02:00
Samuel Pitoiset 17e79865cf radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS
The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
it was initialized to 0.

COMPUTE_RESOURCE_LIMITS is correctly set when generating
compute pipelines, so we don't need to initialize it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-15 16:20:38 +02:00
Andres Gomez 53b4701cb0 docs: update calendar 18.2.0-rc3 is out
Signed-off-by: Andres Gomez <agomez@igalia.com>
2018-08-15 15:48:18 +03:00
Mauro Rossi 43318d5857 radv/meta_decompress: fix pointer to integer conversion
VK_NULL_HANDLE replaces NULL to avoid following building error:

external/mesa/src/amd/vulkan/radv_meta_decompress.c:365:54: error:
incompatible pointer to integer conversion passing 'void *' to parameter
of type 'VkShaderModule' (aka 'unsigned long long') [-Werror,-Wint-conversion]
                VkResult ret = create_pipeline(cmd_buffer->device, NULL, samples,
                                                                   ^~~~
prebuilts/clang/host/linux-x86/clang-4053586/lib64/clang/5.0.300080/include/stddef.h:105:16:
note: expanded from macro 'NULL'
#  define NULL ((void*)0)
               ^~~~~~~~~~
external/mesa/src/amd/vulkan/radv_meta_decompress.c:97:32:
note: passing argument to parameter 'vs_module_h' here
                VkShaderModule vs_module_h,
                               ^
1 error generated.

Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-15 14:34:50 +02:00
Mauro Rossi 73b342c7a5 egl/android: fix regression in drm_gralloc path (v2)
This patch fixes a regression in mesa 18.2 and mesa-dev branches
for HAVE_DRM_GRALLOC code path which is causing black screen on Android
and prevents boot due to SIGSEGV MAPERR crash related to unproper handling
of drm_gralloc drm FD in new droid_open_device() path.

Problem is due to c7bb82136b ("egl/android: Add DRM node probing and filtering")

To avoid the crash the former existing working droid_open_device() is restored,
renamed droid_open_device_drm_gralloc() and kept within HAVE_DRM_GRALLOC braces.

Tested with mesa-dev and mesa 18.2 branch and oreo-x86 bootanimation
and Androdi GUI booting is fixed with i965, nouveau, radeon.
The changes are compatible with gbm_gralloc, I've tested build with hwc too.

(v2) remove indentation from HAVE_DRM_GRALLOC pre-processor directive

NOTE: Definition of enum{} for GRALLOC_MODULE_PERFORM_GET_DRM_FD
is not necessary and it's actually causing a redefinition building error,
because in HAVE_DRM_GRALLOC path gralloc_drm.h is already exported
by libgralloc_drm which is currently still a dependency.

Fixes: c7bb82136b ("egl/android: Add DRM node probing and filtering")
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
2018-08-15 14:07:49 +02:00
Tapani Pälli 656ccf4ef8 mesa: shader dump/read support for ARB programs
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106283
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2018-08-15 11:03:35 +03:00
Danylo Piliaiev 479a849ad6 glsl: Avoid calling get_array_element for scalar constants
Accessing scalar constant as an array in function call or
initializer list triggered assert in get_array_element.
Examples:
   func(0[0]);
   vec2 t = { 0[0], 0 };

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107550

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-08-15 10:01:43 +03:00
Marek Olšák bffa025ada radeonsi: enable 1 missing PS_SU perf counter on Polaris 2018-08-14 21:20:31 -04:00
Marek Olšák df50099834 radeonsi: use radeon_info::name
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-08-14 21:20:31 -04:00
Marek Olšák 84652721b9 ac: add radeon_info::name
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-08-14 21:20:31 -04:00
Marek Olšák de8d5edbc4 radeonsi: split si_clear_buffer to remove enum si_method
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:21:12 -04:00
Marek Olšák 4de92f2abb radeonsi: replace CP_DMA_USE_L2 with enum si_cache_policy
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:21:10 -04:00
Marek Olšák bc132d62f9 radeonsi: declare coher in si_copy_buffer
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:21:09 -04:00
Marek Olšák cddd7ce325 radeonsi: make PFP_SYNC_ME an explicit CP DMA flag
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:21:07 -04:00
Marek Olšák 277295962c radeonsi: don't use emit_data->args in load_emit
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:21:06 -04:00
Marek Olšák 8fb34050b5 radeonsi: don't use emit_data->args in store_emit
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:21:04 -04:00
Marek Olšák a2c18bfbe3 radeonsi: don't use emit_data->args in atomic_emit
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:21:03 -04:00
Marek Olšák 297fb213b3 radeonsi: don't use emit_data->args in build_interp_intrinsic
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:21:01 -04:00
Marek Olšák 99ae440d4e radeonsi: inline atomic_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:59 -04:00
Marek Olšák 267e92893c radeonsi: inline store_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:58 -04:00
Marek Olšák f15e55aa8a radeonsi: inline load_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:56 -04:00
Marek Olšák 2c94f321eb radeonsi: merge txq_emit and resq_emit
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:55 -04:00
Marek Olšák a14c803166 radeonsi: inline resq_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:54 -04:00
Marek Olšák 347e52adcd radeonsi: inline txq_fetch_args
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:52 -04:00
Marek Olšák c9b2ce2672 radeonsi: use get_resinfo directly in lower_gather4_integer
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:36 -04:00
Marek Olšák 7804ddaf87 radeonsi: inline tex_fetch_args into build_tex_intrinsic
The diff looks like it moves code that I didn't touch.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:34 -04:00
Marek Olšák da1d8adc29 radeonsi: remove fetch_args callbacks for ALU instructions
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:33 -04:00
Marek Olšák ac72a6bd0b radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.c
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:20:31 -04:00
Marek Olšák 0ca8294ece radeonsi: implement EXT_window_rectangles
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:19:02 -04:00
Marek Olšák 465e929d6a gallium/u_blitter: save/restore window rectangles
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:19:01 -04:00
Marek Olšák 15fc0f8d4a noop: implement set_window_rectangles
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:18:59 -04:00
Marek Olšák 7c8716e4fb ddebug: implement set_window_rectangles
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 21:18:51 -04:00
Rodrigo Vivi 44f1dcf9b3 i965: Add a new CFL PCI ID.
One more CFL ID added to spec.

Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl:
Add a new CFL PCI ID.")

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-14 15:46:56 -07:00
Rob Clark 70bf639328 freedreno/ir3: add support for a6xx 'merged' register set
Starting with a6xx, half and full precision registers conflict.  Which
makes things a bit more efficient, ie. if some parts of the shader are
heavy on half-precision and others on full precision, you don't have to
allocate the worst case for both.  But it means we need to setup some
additional conflicts.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-14 17:59:02 -04:00
Rob Clark 4813060ed4 freedreno/ir3: small RA cleanup
Collapse is_temp() into it's only callsite, and pass compiler object as
struct rather than void.  Just cleanups to reduce noise in next patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-14 17:59:02 -04:00
Rob Clark fdd35f497b freedreno/ir3: stop hard-coding FS input regs
We originally did this because at the time we didn't know all the
bitfields to configure where various frag shader sysval's went.  But
we do.

So switch to using sysvals for all the frag shader inputs.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-14 17:59:02 -04:00
Rob Clark e97b56172c freedreno/ir3: use r63.x for unused inputs
This way, unused sysval inputs, like frag_vcoord, get the correct regid
value to disable the input.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-14 17:59:02 -04:00
Rob Clark 066930e54d freedreno/ir3: create all inputs in first block
create_input()/create_input_compmask() should take the ctx as arg,
rather than block, to enforce that all inputs are created in the first
block, so that RA sees them as live at the start of the shader.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-14 17:59:02 -04:00
Rob Clark 62da068fd3 freedreno/ir3: rename s/frag_pos/frag_vcoord/g
Make it more clear that this is varying fetch related.  Also fixup some
comments.  Just cleanup for next patches.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-14 17:59:02 -04:00
Rob Clark 4a7f9feada compiler: add SYSTEM_VALUE_VARYING_COORD
Used internally in freedreno/ir3 for the vec2 value that hw passes to
shader to use as coordinate for bary.f (varying fetch) instruction.
This is not the same as SYSTEM_VALUE_FRAG_COORD.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-14 17:59:02 -04:00
Rob Clark b5a098b202 freedreno/ir3: move per-generation compiler config
Move it from the compile ctx to the compiler object, before adding
new things for a6xx.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-14 17:59:02 -04:00
Bas Nieuwenhuizen 66e12451ac radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.
Behavior wrt firstInstance got changed, and a divisor of 0 has been
disallowed.

The new version of the ext got published in specification 1.1.81.

Sending to stable since the only known user is DXVK, which needs
this for correctness.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: 18.2 <mesa-stable@lists.freedesktop.org>
2018-08-14 22:13:09 +02:00
Bas Nieuwenhuizen 4bb6c49375 radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.
Follow radeonsi.

Fixes: 3665f66ef2 "radv: Add support for ETC2 textures."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 22:11:04 +02:00
Bas Nieuwenhuizen bf33ca7512 radv: Fix missing Android platform define.
CC: <mesa-stable@lists.freedesktop.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14 22:11:04 +02:00