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Kenneth Graunke e79e1ca304 intel: Drop Tigerlake revision 0 workarounds 
Tigerlake revision 0 is an early stepping that should not be used in
production anywhere, so this code was only used for hardware bringup.
We can drop the unnecessary workarounds.  This also keeps them from
triggering on early steppings of other Gfx12 parts.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13266>
 2021-10-21 16:53:43 -07:00
Marek Olšák 6ef192bddf mesa: discard draws with count=0 to decrease overhead 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13445>
 2021-10-21 21:16:13 +00:00
Nanley Chery 7daff157bb iris: Refactor the assignment to possible_usages 
* Make the outer if-ladder dependent on the has_* variables.
* Make the possible_usages assignments happen at the same nesting level.
* Move the combined HIZ/MCS assert closer to relevant if-else blocks.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11960>
 2021-10-21 20:21:26 +00:00
Nanley Chery 114f87c1c7 iris: Set DISABLE_AUX_BIT for AUX_USAGE_NONE modifiers 
This avoids unnecessary surface padding on TGL+.

Also, drop some of the logic to handle modifiers in
iris_resource_configure_aux as the bit now causes it to be handled
implicitly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11960>
 2021-10-21 20:21:26 +00:00
Nanley Chery b9d8793646 iris: Disable the MC_CCS modifier with norbc 
We generally try to disable CCS whenever the norbc debug flag is set.
Also, this enables simplifying iris_resource_configure_aux later on.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11960>
 2021-10-21 20:21:26 +00:00
Nanley Chery b71264e465 iris: Convert some mod_info checks to asserts 
Depth and multisample images aren't supported with modifiers. So,
instead of checking for the absence of modifiers before adding HiZ or
MCS, simply assert that they aren't present at a more convenient time.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11960>
 2021-10-21 20:21:26 +00:00
Rob Clark 138be96301 freedreno/ir3: Fix validation of subgroup macros 
They don't need to enforce that src types are all the same.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark e68d918ffb freedreno/ir3: Get req_local_mem from pipe_compute_state 
mesa/st initializes req_local_mem to shader->info.shared_size.  But for
clover the shared size doesn't come from the shader.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f58438320c freedreno/ir3: Add ihadd/uhadd 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f5ce806ed7 freedreno/ir3: Add wide load/store lowering 
Lower load/store for vectors wider than 4.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 7a7ac8cd40 freedreno/ir3: Fix reg size validation 
8b types also live in half-regs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 8a6934dfe8 freedreno/ir3: Fix load/store_global_ir3 type 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 81eefe0090 freedreno/ir3: 8bit fixes 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f7b2d613c5 freedreno/ir3: 16b bools 
A create_immed_for_instr() type thing could be useful to make the immed
type match other src(s) for instruction..

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 9a2562a545 freedreno/ir3: Deal with zero-source instructions 
Needed by the next patch, which starts treating bools as 16bit exposing
a bug that was previously accidentially hidden for instructions like
ELECT_MACRO.  Needed for next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark b6e11225a2 freedreno: Fix set_global_binding 
The gallium interface is a bit awkward, but pointer sizes are actually
64b despite what the API suggests.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 0a35ba5c43 freedreno/ir3: Move lower_idiv_options 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark e544a9db16 freedreno/ir3: Add support for load_kernel_input 
Used for function arguments to compute kernels (ie. OpenCL).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark e10c76d277 freedreno/ir3: implement load_work_dim intrinsic 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 3bd265a393 freedreno/ir3: vec8+vec16 support 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f5bbf77be8 freedreno: implement set_compute_state() 
This interface should really go away, but for now just implement it
to directly update constant state (ie. what clover *should* be doing
instead)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 1e9f27f37f freedreno/ir3: Handle MESA_SHADER_KERNEL 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 83a1bca952 freedreno: Skip built-in shaders for clover 
Avoids assert:

  ../src/compiler/glsl_types.cpp:1134: static const glsl_type *glsl_type::get_array_instance(const glsl_type *, unsigned int, unsigned int): Assertion `glsl_type_users > 0' failed.

caused by us trying to compile built-in shaders (ie. clear, gmem<->mem,
etc) before clover has initialized glsl_types.  But we don't need these
shaders for compute-only contexts.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev dff8a0c4cb isaspec: inherite parent's bitset gpu gen requirements 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark d77b9fb518 isaspec: Fix gpu_id for default_options 
We forgot to set this.  It starts to matter in the next patch, otherwise
pre-pass to detect branch targets (needed for backwards jumps/branches)
will not work.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev c4e7541b9d freedreno/ir3: use stg.a/ldg.a only if offset is reg or doesn't fit 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 064c806d23 freedreno/ir3: Add load/store_global lowering 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev d85eb9268a freedreno/ir3: set proper dst size for {store,load}_{global,shared}_ir3 
We want to pass 64b variables.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev 1ef43a0be7 freedreno/ir3: disallow immediate addr/offset for ldg/ldg.a 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f45b7c58c4 freedreno/ir3: Lower 64b phis 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev bee9212efb ir3/freedreno: add 64b undef lowering 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 2d65e6f56d freedreno/ir3: 64b intrinsic lowering 
Both for OpenCL and VK_KHR_buffer_device_address

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev 1eee1fda11 nir/lower_amul: do not lower 64bit amul to imul24 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Sagar Ghuge b83c9b21a6 intel/compiler: Set correct cache policy for A64 byte scattered read 
This doesn't impact any performance since the previous typo value
matches the current cache control value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13458>
 2021-10-21 17:32:23 +00:00
Marek Olšák 272af39be1 amd/addrlib: cosmetic addrlib update 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13459>
 2021-10-21 16:26:06 +00:00
Marek Olšák 69a1b02b68 amd/addrlib: change how the license is formatted to match internal tree 
It's the same MIT license.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13459>
 2021-10-21 16:26:06 +00:00
Sajeesh Sidharthan cf0bc4fb55 frontends/va/av1: handle multiple slice params 
Multiple slice params in a single vaRenderPicture function call
is not handled. This patch will fix overwriting slice params
when multiple slice params received in one buffer.

Change-Id: I880df5bc35dfbd64382a178074482548882ee4af
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13463>
 2021-10-21 16:12:30 +00:00
Samuel Pitoiset 996e81fb70 aco: fix loading 64-bit inputs with fragment shaders 
Fixes a bunch of 64-bit IO tests with piglit and Zink.

Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13454>
 2021-10-21 12:50:55 +02:00
Iago Toral Quiroga 75bd37dc6a broadcom/compiler: disallow tsy barrier in thrsw delay slots 
A TSY barrier becomes effective at the point of the next thread switch,
so if we have one coming after a previous thread switch we need to
be careful not to emit it in its delay slots, or we would be effectively
moving the barrier earlier than intended.

Fixes simulator assert crash in:
dEQP-VK.graphicsfuzz.two-for-loops-with-barrier-function

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13468>
 2021-10-21 12:40:00 +02:00
Emma Anholt 9202e8cbaf turnip: Make copy_format() and tu6_plane_format() return pipe_format 
[ Connor: Keep the argument to copy_format() a VkFormat, fold in
  plane_format() conversion. ]

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13379>
 2021-10-21 08:46:31 +00:00
Emma Anholt 68f8bbb37e util: Move freedreno's snorm-to-unorm to util/, adding remaining cases. 
I want it in turnip too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13379>
 2021-10-21 08:46:31 +00:00
Emma Anholt cbdc8e09bf turnip: Switch format_to_ifmt() to take a pipe_format. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13379>
 2021-10-21 08:46:31 +00:00
Emma Anholt e4e8db0132 turnip: Switch tu6_format_color() to a pipe_format. 
To handle Y8 specially, we want a PIPE_FORMAT instead of VK_FORMAT.  There
are some redundant vk-to-pipe conversions, but they're going to go away
shortly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13379>
 2021-10-21 08:46:31 +00:00
Emma Anholt 3b68fc0c6a turnip: Switch tu6_format_texture() to a pipe_format. 
To handle Y8 specially, we want a PIPE_FORMAT instead of VK_FORMAT.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13379>
 2021-10-21 08:46:31 +00:00
Connor Abbott cfabdbd7d3 tu/clear_blit: Move around copy_format()/tu6_plane_format() 
We want these functions to take a Vulkan format and return a
pipe_format, but tu6_plane_format() was getting redundantly called on
the result of copy_format() and copy_format() was also getting called
twice with image to image copies. Pull these functions further up the
call chain so that they're only called once.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13379>
 2021-10-21 08:46:31 +00:00
Iago Toral Quiroga acb83e1b13 v3dv: enable Vulkan 1.1 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13465>
 2021-10-21 10:12:38 +02:00
Emma Anholt bd81a23620 ci/piglit-runner: Fix funny indentation of the piglit-runner command. 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13372>
 2021-10-21 07:34:19 +00:00
Emma Anholt 440f207a1f ci/deqp-runner: Move more non-suite logic under the non-suite 'if'. 
Changing these variables won't do anything for you otherwise.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13372>
 2021-10-21 07:34:19 +00:00
Emma Anholt 92748e40ef ci/deqp-runner: Don't start GPU hang detection for making junit results. 
It's just CPU-side post-processing, not running tests.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13372>
 2021-10-21 07:34:19 +00:00
Emma Anholt 61ca900b69 ci/deqp-runner: Drop LD_LIBRARY_PATH=/usr/local for libkms workaround. 
deqp hasn't been linking against that in quite some time.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13372>
 2021-10-21 07:34:19 +00:00