df64122c30
fbdev: some hacking to get the driver to compile (untested)
2010-05-27 09:46:32 -06:00
a4bd52adba
update linux-fbdev config
2010-05-27 09:46:21 -06:00
3644dbbdbd
vbo: comments and whitespace
2010-05-27 09:40:33 -06:00
4225c4e1b0
vbo: remove unused prototype
2010-05-27 09:40:33 -06:00
9aae67ca3a
vbo: remove dead code
2010-05-27 09:40:33 -06:00
b6187057be
vbo: update/add comments
2010-05-27 09:40:33 -06:00
f49a65628f
mesa: Remove unnecessary headers.
2010-05-27 08:10:31 -07:00
6e9da8ab60
egl: Return NULL if we fail to load a default driver
2010-05-27 09:59:27 -04:00
7d7bdee50d
mesa: remove unused includes
2010-05-26 22:42:13 -06:00
eb88c02a4b
mesa: rewrite _mesa_get_handle() and add some comments
2010-05-26 22:40:38 -06:00
69861ae497
mesa: move GLSL uniform functions into new source file
2010-05-26 22:30:10 -06:00
655c9a0533
st/mesa: Remove unnecessary headers.
2010-05-26 20:12:33 -07:00
055750fafb
Enable hardware mipmap generation for radeon.
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Use _mesa_meta_GenerateMipmap. It is Fast Enough(tm).
Signed-off-by: Maciej Cencora <m.cencora@gmail.com >
Signed-off-by: Alex Deucher <alexdeucher@gmail.com >
2010-05-26 18:17:28 -04:00
a9ee956511
Fix image_matches_texture_obj() MaxLevel check
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When generating or uploading a new (higher) mipmap level for an image,
we can need to allocate a miptree for a level greater than
texObj->MaxLevel.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com >
Signed-off-by: Alex Deucher <alexdeucher@gmail.com >
2010-05-26 18:17:28 -04:00
f49da110a8
Fallback to software render if there is no miptree for an image
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This can happen when checking if a software fallback for a higher level
operation (such as GenerateMipmap) is needed.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com >
Signed-off-by: Alex Deucher <alexdeucher@gmail.com >
2010-05-26 18:17:28 -04:00
76034aaf65
r300g: decouple drawing code and two-sided stencil refvalue fallback
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It's now more separate from the rest of the driver and it can be disabled
by commenting out just 1 line. Well, I couldn't make the previous version
work with SW TCL reliably, that's the reason of this little rework.
2010-05-27 00:08:42 +02:00
1345c5bf94
r300g/swtcl: handle large index count properly
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This fixes piglit/draw-elements.
2010-05-26 22:39:19 +02:00
3a6fd21917
r300g/swtcl: force vertex prefetching for non-indexed primitives
2010-05-26 22:22:52 +02:00
55a6d37434
r300g/swtcl: move emitting AOS to prepare_for_rendering
2010-05-26 22:22:52 +02:00
500160a3c9
r300g/swtcl: vbo transfer sanity checks
2010-05-26 22:22:52 +02:00
a81730cb32
r300g: add get_cs_info winsys entrypoint, abandon check_cs
2010-05-26 22:22:52 +02:00
6ca3f86bdc
r300g/swtcl: do not use u_upload_mgr and do not compute max_index
2010-05-26 22:22:52 +02:00
bbfd785259
r300g: remove unnecessary includes
2010-05-26 22:22:52 +02:00
3b68b6c83e
i965: Add support for EXT_timer_query on Ironlake.
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We could potentially do this on G45 as well, though the units are
different. On 965, the timestamp is tied to hclk, which would make
supporting it harder.
2010-05-26 12:14:44 -07:00
fd3425fdff
intel: Handle decode of PIPE_CONTROL instructions.
2010-05-26 12:13:54 -07:00
ddb10c3e60
i965: Move Gen6 debugging emit_mi_flush into the Gen6 block.
2010-05-26 12:13:54 -07:00
8f61114907
i965: Don't PIPE_CONTROL instruction cache flush.
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This is a workaround for Ironlake errata. The emit_mi_flush is used
for a few purposes:
1) Flushing write caches for RTT (including blit to texture)
2) Pipe fencing for sync objects
3) Spamming cache flushes to track down cache flush bugs
Spamming cache flushes seems less important than following the docs,
and we should probably do that with a different mechanism than the one
for render cache flushes.
2010-05-26 12:13:54 -07:00
6e2330daa6
i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.
2010-05-26 12:13:54 -07:00
80689ae615
gallivm: Remove unnecessary headers.
2010-05-26 11:13:23 -07:00
2966a25d3b
st/xorg: Remove unnecessary headers.
2010-05-26 10:59:57 -07:00
3fa8a8ea28
util: Remove unnecessary headers.
2010-05-26 10:53:54 -07:00
67d5a51021
st/dri: Remove dri.c from SCons build.
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This was missed in commit f501230db3
2010-05-26 10:24:36 -07:00
cee4220f16
Revert the 'make static' part of 962f926112
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The es1 and es2 dispath table initialization code is generated from the
API XML files and we can't easily share the dispatch table code setup.
Keep the _mesa_init_shader_dispatch() part of the patch, but roll back
the static-ization of shader entrypoints so es1 and es2 dispatch
initialization still works.
2010-05-26 11:32:36 -04:00
1bdbc0e38f
r300g: fix fence referencing
2010-05-26 16:39:32 +02:00
d3f598a506
mesa: move all vertex array functions into varray.c
2010-05-25 21:42:13 -06:00
a830eef8c2
mesa: added _mesa_GetVertexAttribIiv / AttribIuiv()
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Refactor the code for all the glGetVertexAttrib() functions.
2010-05-25 21:38:02 -06:00
e00d07cff6
mesa: added _mesa_VertexAttribIPointer()
2010-05-25 21:18:33 -06:00
e793a24d7c
mesa: new GL 3.0 VertexAttrib commands
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Still need to plug in API dispatch...
2010-05-25 21:18:33 -06:00
962f926112
mesa: make a bunch of shader API functions static
2010-05-25 21:18:33 -06:00
a017c7ecb7
mesa: display list support for uint uniforms
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Still need to plug into dispatcher...
2010-05-25 21:18:33 -06:00
09c7d7bf2a
mesa: consolidate some glUniform code
2010-05-25 21:18:32 -06:00
07b0529e55
mesa: unsigned int uniform functions (GL3)
2010-05-25 21:18:32 -06:00
91f841aefc
mesa: support for unsigned int uniforms
2010-05-25 21:18:32 -06:00
f0896e7f80
r300/compiler: implement SGT+SLE opcodes
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Reported-by: Gianluca Anzolin <gianluca@sottospazio.it >
2010-05-26 04:47:55 +02:00
49bac3ccd8
r300/compiler: fix dumping r5xx vertex shaders
2010-05-26 04:47:27 +02:00
5c067a6304
r300/compiler: move hardware caps to the radeon_compiler base struct
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Needed for vertex shaders too.
2010-05-26 04:47:26 +02:00
f2582da3bb
r300/compiler: shorten swizzle expressions
2010-05-26 04:47:26 +02:00
15496e06b7
rbug: add set sample mask passthrough.
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This at least stops rbug segfaulting at startup.
Signed-off-by: Dave Airlie <airlied@redhat.com >
2010-05-26 11:45:32 +10:00
e6a8513a86
r300g: more efficient finish + fix comments
2010-05-26 01:41:32 +02:00
2c072c8f72
r300g: implement fake but compliant fences
2010-05-26 01:23:11 +02:00
Brian Paul