Jason Ekstrand
d82cea5fc3
genxml: Add BVH data structures
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908 >
2022-08-05 11:51:31 +00:00
Marcin Ślusarz
f4386b81e6
intel: fix typos found by codespell
...
Acked-by: David Heidelberg <david.heidelberg@collabora.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191 >
2022-06-27 10:20:55 +00:00
Kenneth Graunke
b05ac36f01
intel/genxml: Add SAMPLER_MODE bits for enabling Small PL on Icelake
...
This enables a lower power mode in the sampler hardware in certain
common scenarios. On Tigerlake, SAMPLER_MODE is not programmable by
userspace but the kernel already sets this bit for us.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628 >
2022-04-11 19:17:07 +00:00
Kenneth Graunke
e3defe7ae7
intel/genxml: Delete SAMPLER_MODE register definition on Gfx12+
...
While this register still exists, it's no longer a per-context register.
Instead, on Gfx12+, SAMPLER_MODE exists per dual-subslice and is
accessed as a "multicast" register, where you write control which
version is accessed by the "steering control register".
At any rate, userspace cannot write it any longer, and so there's not
much point to it existing in our genxml (which was missing most of the
fields anyway).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628 >
2022-04-11 19:17:07 +00:00
Kenneth Graunke
8092704705
intel/genxml: Add new "Low Quality Filter" field on Gfx12+.
...
This allows the sampler to perform faster filtering of 8-bit UNORM
textures by filtering them at a different precision. The filtering
is intended to still be OpenGL and DirectX spec compliant.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628 >
2022-04-11 19:17:07 +00:00
Kenneth Graunke
9a70385e2b
intel/genxml: Add SAMPLER_STATE::Allow Low Quality LOD Calculation field
...
This allows the hardware to perform a faster LOD calculation in many
simple cases.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628 >
2022-04-11 19:17:07 +00:00
Lionel Landwerlin
88f77aa811
anv: disable preemption on 3DPRIMITIVE on gfx12
...
To workaround a push constant corruption issue.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5963
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5662
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15753 >
2022-04-06 12:51:15 +00:00
Lionel Landwerlin
2763a8af5a
anv/genxml/intel/fs: fix binding shader record entry
...
Bit is flipped compared to all the other packets.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 705395344dc3ac9afca3jason.ekstrand@collabora.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15078 >
2022-02-19 13:50:56 +00:00
Tapani Pälli
442628b702
intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
...
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815 >
2022-02-09 10:05:10 +00:00
Kenneth Graunke
d2646e147b
intel/genxml: Add missing MI_FLUSH_DW::Flush CCS field
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14912 >
2022-02-07 09:50:01 -08:00
Emma Anholt
dbcdededb2
intel: Add missing dep of gen_*_header.py on utils.py.
...
Reviewed-by: Dylan Baker <dylan@pnwbakers.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725 >
2022-02-02 11:21:57 -08:00
Caio Marcelo de Oliveira Filho
b01c73fd0a
intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH
...
And corresponding value in XML.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
Lionel Landwerlin
665ffd4bf9
anv: Update VK_KHR_fragment_shading_rate for newer HW
...
Per primitive & attachment shading rate support added.
v2: Rebase on KHR_dynamic_rendering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
Lionel Landwerlin
dff08cbf8e
isl: add support for coarse pixel control surfaces
...
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.
v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)
v3: Drop unused macro (Nanley)
s/isl_to_gen/isl_encode/ (Nanley)
Remove pitch alignment 128B constraint already covered by tiling (Nanley)
Move some asserts together (Nanley)
v4: Disable miptail for now (Nanley)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
Lionel Landwerlin
8bdbc93a9d
genxml: add new 3DSTATE_PS_EXTRA bit
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
Lionel Landwerlin
ea71fb0b4b
genxml: gen12.5 changes for CPS
...
v2: Make genxml look more like BSpec (Caio)
Fixup X_Focal/Y_Focal entries (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739 >
2022-02-02 17:09:46 +00:00
Nanley Chery
fde43bb194
intel: Rename a RenderCompressionFormat field
...
The name of the bit field is CompressionFormat. The format subsections
of the field specify the alternate names of RenderCompressionFormat or
MediaCompressionFormat depending on the compression type.
We're going to start programming this field for media compression, so
we'd like to use either the bit field name or a new
MediaCompressionFormat field. Either option seems fine, so we go with
the first.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355 >
2022-01-28 00:30:55 +00:00
Jordan Justen
8db5937f94
intel/genxml: Extend length of 3DSTATE_DEPTH_BUFFER for gfx12.5
...
The two added dwords are MBZ.
Ref: bspec 46935
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14702 >
2022-01-26 00:22:54 +00:00
Jordan Justen
315d632977
intel/genxml: Extend length of 3DSTATE_WM_HZ_OP for gfx12.5
...
The added dword is MBZ.
Ref: bspec 46981
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14702 >
2022-01-26 00:22:54 +00:00
Kenneth Graunke
3e0bffbad3
intel/genxml: Add XY_BLOCK_COPY_BLT Color Depth enum values
...
Requested by Jason.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687 >
2022-01-24 23:27:25 +00:00
Sagar Ghuge
c0849a0697
intel/genxml: Add Un-Typed Data-Port Cache Flush field to pipe control
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14676 >
2022-01-23 23:46:54 -08:00
Sagar Ghuge
08429da731
intel/genxml: Add L1 Cache Control bit field
...
Add L1 cache control bit field to RENDER_SURFACE_STATE and
STATE_BASE_ADDRESS instruction.
v1: (Jason)
- Add prefix to bit field
- Don't miss out STATE_BASE_ADDRESS instruction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14676 >
2022-01-23 23:43:28 -08:00
Nanley Chery
f960e398d3
intel/gen125.xml: Increase Auxiliary Surface Pitch
...
See Bspec 43862.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Acked-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464 >
2022-01-21 20:38:05 +00:00
Lionel Landwerlin
51f6288a2d
genxml: reduce amount of generated code
...
$ wc -l build/src/intel/genxml/genX_bits.h
250581 build/src/intel/genxml/genX_bits.h (before)
5748 build/src/intel/genxml/genX_bits.h (after)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Acked-by: Kenneth Graunke <kenneth@whitecape.org >
Acked-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14469 >
2022-01-19 10:57:48 +00:00
Nanley Chery
8ec8298ce4
intel: Rename the PSD bit in PIPE_CONTROL for XeHP
...
The name of the field now starts with PSS Stall instead of PSD.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024 >
2022-01-12 01:30:34 +00:00
Francisco Jerez
074bde9989
intel/xehp: Switch to coarser cross-slice pixel hashing with table permutation.
...
The coarser 32x32 cross-slice hashing mode seems to lead to better L1
and L2 utilization due to the improved execution locality, however it
can also lead to a bottleneck in a single slice, especially in
workloads that concentrate heavy rendering in small areas of the
screen (e.g. SynMark2 OglGeomPoint, OglTerrain*) -- This effect is
mitigated here by performing a permutation of the pixel pipe hashing
tables that ensures that adjacent rows map to pixel pipes as far away
as possible in the caching hierarchy.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
Francisco Jerez
ae5fa3f518
intel/genxml: Fix SLICE_HASH_TABLE struct on XeHP.
...
It's now an array with 7 tables, each table is intended to specify the
pixel pipe hashing behavior for every possible slice count between 2
and 8, however that doesn't actually work, among other reasons due to
hardware bugs that will cause the GPU to erroneously access the table
at the wrong index in some cases, so in practice all 7 tables need to
be initialized to the same value.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:27:41 -08:00
Dave Airlie
a2293e33fd
intel/genxml/gen4-5: fix more Raster Operation in BLT to be a uint
...
This has been partly fixed twice before, but looks like some got missed.
Fixes arb_copy_image on gen4 with crocus
Fixes: de625dddeejason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14345 >
2021-12-30 11:40:33 +10:00
Jordan Justen
1ed7a65e6d
intel/genxml/12.5: Remove bt-pool enable from 3DSTATE_BINDING_TABLE_POOL_ALLOC
...
This was dropped in gfx12.5.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992 >
2021-12-20 17:58:13 +00:00
Lionel Landwerlin
d44478483c
genxml: protect _length defines in genX_bits.h
...
Those defines exist in the packing headers too and some parts of the
code (like mi_builder.h) include both.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13954 >
2021-12-06 08:02:59 +00:00
Lionel Landwerlin
e9b58116ea
genxml: fix compilation with P/I defines
...
Those names are a bit too common and sometimes clash variables.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13954 >
2021-12-06 08:02:59 +00:00
Kenneth Graunke
88e4d3809c
intel/genxml: Decode VALIGN/HALIGN values in XY_BLOCK_COPY_BLT
...
For easier readability in INTEL_DEBUG=bat.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809 >
2021-11-16 11:38:30 +00:00
Kenneth Graunke
406ff7473a
intel/genxml: Fix XY_BLOCK_COPY_BLT destination tiling field type
...
Fixes: 2f58a63b2flionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809 >
2021-11-16 11:38:30 +00:00
Kenneth Graunke
29025f66fd
intel/genxml: Fix MI_FLUSH_DW to actually specify the length properly
...
Fixes: 569afd37f1lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809 >
2021-11-16 11:38:30 +00:00
Kenneth Graunke
ebc0099d89
intel/genxml: Collapse leading underscores on prefixed value defines
...
We prefix names with an underscore to make them "safe" C identifiers
when necessary. For example, a value of "32x32" would become "_32x32".
However, when specifying something like
<field ... prefix="BLOCK_SIZE">
<value name="32x32" value="0"/>
</field>
we already have a prefix that makes the field name safe. We'd rather
generate a name with a single underscore, i.e.
#define BLOCK_SIZE_32x32 0
rather than
#define BLOCK_SIZE__32x32 0
This also fixes up affected defines in crocus.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809 >
2021-11-16 11:38:30 +00:00
Kenneth Graunke
cd7d3c7ae3
intel/genxml: Simplify prefix handling for field value lists
...
When a <field> tag has multiple <value> children, listing symbolic names
for possible field values, we generate #defines for each value, with an
optional prefix. I don't know why, but this code was checking whether
self.default is None. We want to generate the same list of #defines,
with a prefix, regardless of whether the field has a default value
specified or not.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809 >
2021-11-16 11:38:30 +00:00
Dave Airlie
bf7b6dd73f
intel/genxml: generate video headers
...
This just generates the video engine pieces.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
Dave Airlie
8f9006804a
intel/genxml: fix gen6 LD->VLD typo.
...
Pointed out by Ilia
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
Matt Turner
2bb8aa2942
intel/genxml: capitalize decoder mode select properly
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
Dave Airlie
2268fc1bb6
intel/genxml: fix Picure->Picture typo
...
Ilia pointed this out.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
Dave Airlie
dc32a164c8
intel/genxml: align QM field names across gens.
...
This just picks a consistent name.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
Dave Airlie
0f3f8b4591
intel/genxml: fix some missing address from the 75 xml
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
Dave Airlie
5d956d65b6
intel/genxml: cleanup video xml collisions.
...
When you enable video genxml, lots of warnings about redefined things
appear, just clean those up before things get started.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
Jordan Justen
a298ad26c1
intel/genxml/125: Update COMPUTE_WALKER POSTSYNC_DATA struct
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13624 >
2021-11-08 23:29:51 +00:00
Caio Oliveira
3567d47f3e
intel/genxml: Inline the BODY structs into the instructions
...
Follows the convention used in other instructions.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13657 >
2021-11-04 21:01:13 +00:00
Caio Oliveira
3fe2e862b5
intel/genxml: Add Mesh Shading structures
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13657 >
2021-11-04 21:01:13 +00:00
Kenneth Graunke
2f58a63b2f
intel/genxml: Add XY_BLOCK_COPY_BLT on Tigerlake and later.
...
This is a new blitter command introduced on Tigerlake and expanded
substantially on XeHP. XY_BLOCK_COPY_BLT is actually fast, unlike
the legacy blitter commands. iris will use this in the future, and
anv hopefully could use it for a transfer queue someday as well.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520 >
2021-10-28 14:17:32 -07:00
Kenneth Graunke
9163500aa1
intel/genxml: Allow MI_FLUSH_DW on the blitter
...
Pretty sure this is how you flush the blitter.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520 >
2021-10-28 14:17:32 -07:00
Kenneth Graunke
d9ffdfc16d
intel/genxml: Include blitter commands in gen*_pack.h
...
We're going to want to use the blitter again on newer hardware,
which means we need to be able to use genxml to emit those commands.
Acked-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520 >
2021-10-28 14:17:29 -07:00
Kenneth Graunke
7b78b2fcac
intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+
...
Let's try and catch performance problems before we have to do large
painful amounts of analysis to detect a missed field.
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480 >
2021-10-28 19:45:56 +00:00
