Mary Guillemard
becccebd21
nvk: Use MEM_LOCAL for nvk_cmd_mem_create
...
It is safe to allocate command buffer memory as MEM_LOCAL (VRAM or GART)
when we can map GPU memory (we trust NVKMD to force GART).
This reduces latency on pyrowave for compute dispatch (~1.90ms -> ~1.48ms),
likely as QMD and the root tables should not have been in GART in the first place.
Signed-off-by: Mary Guillemard <mary@mary.zone >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36970 >
2025-08-26 21:25:08 +00:00
Mary Guillemard
5d77057ff6
nvk: Force GART for command buffers
...
We are already always allocating on GART at the moment, let's force it
for now as we are going to change the default.
Signed-off-by: Mary Guillemard <mary@mary.zone >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36970 >
2025-08-26 21:25:08 +00:00
Alexandros Frantzis
67f9aac728
egl/wayland: Support pbuffer surfaces
...
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13454
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36064 >
2025-08-26 20:03:23 +00:00
Tapani Pälli
ad2ef16198
iris/anv: toggle on CACHE_MODE_0::MsaaFastClearEnabled on BMG G31
...
This increases rate of depth fast clear rate on BMG G31
per HSD 22020044224.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35966 >
2025-08-26 19:35:34 +00:00
Tapani Pälli
c65f5cd36d
intel/dev: provide a helper to detect bmg g31 device
...
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35966 >
2025-08-26 19:35:33 +00:00
Tapani Pälli
2c9bc313a0
intel/genxml: update CACHE_MODE_0 register for gfx200
...
Field that we currently utilize does not change place, however
there are some new fields so let's update contents to match spec.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35966 >
2025-08-26 19:35:33 +00:00
Eric R. Smith
9b4eb81162
panvk: revised occlusion query pointer fix
...
It turns out that the `occlusion_query.syncobj` is used to set
state that later code relies on, and setting it to NULL causes
some Vulkan CTS tests to fail. Instead, we should explicitly check
for the mode being `MALI_OCCLUSION_MODE_DISABLED` to avoid using
an invalid `ptr` field.
Fixes: 24c692c981lars-ivar.simonsen@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36794 >
2025-08-26 18:42:27 +00:00
Robert Mader
461e3848b9
panfrost: Add lowerings for the NV61, NV24 and NV42 pixel formats
...
For now only add the fallback variants with multiple sampler views in
order to keep things simple.
Signed-off-by: Robert Mader <robert.mader@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36890 >
2025-08-26 18:08:37 +00:00
Robert Mader
6c83ae95a2
mesa: Add support for NV61, NV24 and NV42 pixel formats
...
Which are essentially variants of NV12. All of them have been tested
with the Weston client-buffer test with llvmpipe and radeonsi.
Signed-off-by: Robert Mader <robert.mader@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36890 >
2025-08-26 18:08:37 +00:00
Ahmed Hesham
61fd24c552
rusticl: Fix negative CTS device tests
...
`clRetainDevice` and `clReleaseDevice` ignore the device argument, it
should be checked for validity and return `CL_INVALID_DEVICE` if it
fails.
`check_cl_device_type` fails if entrypoint is passed `0` as the device
type. Zero as an input for a bitwise and operation will always result
in a zero, so the utility function fails to return
`CL_INVALID_DEVICE_TYPE`.
Signed-off-by: Ahmed Hesham <ahmed.hesham@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37008 >
2025-08-26 17:52:40 +00:00
Yiwei Zhang
c4e5661f29
vulkan/android: improve stage masks for semaphore ops
...
Strictly speaking, for an empty batch, there is no inherit/defined
ordering between the wait and signal operations within the batch. We
are relying on MESA impl defined behavior to transfer payloads of the
wait sempahores to the signal sempahore here.
Ideally we need a MESA internal hint to ensure transitivity, but since
this is on the legacy fallback path, it's not worth the effort. So here
we follow common wsi to use TRANSFER_BIT which avoids most unnecessary
stalls on the queue (an improvement over the previous ALL_COMMANDS_BIT).
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36855 >
2025-08-26 17:24:09 +00:00
Yiwei Zhang
d72d0e8580
vulkan/android: skip queue submit with copy_sync_payloads
...
Follows common wsi side for the same reason as explained in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36827
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36855 >
2025-08-26 17:24:08 +00:00
Yiwei Zhang
9ce92584ed
vulkan/runtime: silence a -Wsometimes-uninitialized warning
...
../src/vulkan/runtime/vk_device.c:746:28: warning: variable
'was_signaled' is used uninitialized whenever 'for' loop exits
because its condition is false [-Wsometimes-uninitialized]
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36855 >
2025-08-26 17:24:08 +00:00
Yiwei Zhang
5372fe7cc4
vulkan/android: switch to vkQueueSubmit2
...
This follows common wsi side as suggested, and simplifies the later
adoption of vk_device_copy_semaphore_payloads.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36855 >
2025-08-26 17:24:07 +00:00
Yiwei Zhang
3a5514febf
vulkan/android: add an early return when there's no wait semaphores
...
..and no need to give result a default.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36855 >
2025-08-26 17:24:07 +00:00
Yiwei Zhang
3bf63a7e36
nvk: refactor nvk_CreateImage error path
...
...and fixes some tabs to spaces.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36996 >
2025-08-26 17:09:20 +00:00
Erik Faye-Lund
f9248e81a5
pan/lib: clean up tilebuffer size helpers
...
This way we report the *actual* tilebuffer sizes rather than reporting
twice the amount and then correcting for it later on. The distinction
really only matters on V4 and V6 GPUs, but let's get it correct.
This shouln't have any functional changes, it just makes it easier to
reason about what each GPU supports.
While we're at it, correct the typo in the comment about what gens
supports disabling pipelining. It's *not* supported on V6.
Reviewed-by: Eric R. Smith <eric.smith@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35755 >
2025-08-26 16:21:23 +00:00
Erik Faye-Lund
6a83193771
pan/lib: clamp format size to 4
...
When using formats with less than 32-bits per pixel, we pad the
tile-buffer to a multiple of 32-bits so we can store additional bits
used by dithering.
Account for this when computing the max MSAA setting.
Fixes: 329568b5eberic.smith@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35755 >
2025-08-26 16:21:22 +00:00
Eric R. Smith
37681eef8a
panfrost: add some sanity checks for nr_samples
...
Make sure that depth and color buffers have the same number of
samples. This *should* be guaranteed by the higher levels, but
in the case of a bug we want to notice quickly (and in fact
such a bug has bitten us, see panfrost/mesa/issue#200).
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com >
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36876 >
2025-08-26 15:57:14 +00:00
Aleksi Sapon
a9066c801b
wsi/metal: current extents might not be known until swapchain is created
...
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33518 >
2025-08-26 15:32:41 +00:00
Samuel Pitoiset
b9221c7c89
radv: advertise VK_KHR_shader_untyped_pointers
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36677 >
2025-08-26 13:47:08 +00:00
Samuel Pitoiset
c5a5c8818c
radv/nir/lower_cmat: handle untyped pointers for load/store
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36677 >
2025-08-26 13:47:07 +00:00
Samuel Pitoiset
f08ad89e44
radv: run nir_opt_memcpy before nir_opt_copy_prop_vars
...
Because nir_opt_copy_prop_vars doesn't handle casts well with
nir_intrinsic_memcpy_deref.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36677 >
2025-08-26 13:47:07 +00:00
Samuel Pitoiset
bfd84562a0
radv: run nir_lower_memcpy after spirv->nir
...
To make sure all memcpy are lowered correctly.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36677 >
2025-08-26 13:47:07 +00:00
Jesse Natalie
11bf9ad9ee
d3d12: Only use DComp swapchains when alpha is present in the framebuffer
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36994 >
2025-08-26 13:31:13 +00:00
Jesse Natalie
75d285c2e2
wgl: Always revalidate framebuffer when front is requested
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36994 >
2025-08-26 13:31:13 +00:00
Jesse Natalie
cc017057eb
d3d12: Flush command queue when destroying or resizing
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36994 >
2025-08-26 13:31:13 +00:00
Eric R. Smith
095d1b6bcc
mesa: fix off by one in MSRTT handling
...
The actual number of samples chosen is allowed to equal the number
requested, but currently we just check for sample counts greater
than the request.
Fixes: 894b37e060michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36878 >
2025-08-26 12:24:42 +00:00
Lionel Landwerlin
3362b8dcb5
brw: use a scalar builder for the load_payload on transpose loads
...
I noticed SIMD32 shaders have that kind of pattern :
mov(32) g94<1>D 0D { align1 WE_all };
send(1) g15UD g94UD nullUD 0x6210d500 0x02010000
ugm MsgDesc: ( load, a32, d32, V16, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti ) BTI 2 base_offset 16 { align1 WE_all 1N I@5 $1 };
Why use a 32 wide register for a SEND that is only going to read the first lane?
We can stick a single physical register and reduce register pressure.
DG2 fossils-db results :
Totals:
Instrs: 157417515 -> 157417796 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15362185116 -> 15363086774 (+0.01%); split: -0.05%, +0.05%
Max live registers: 29059141 -> 29051166 (-0.03%)
Max dispatch width: 5071256 -> 5075720 (+0.09%); split: +0.33%, -0.24%
Totals from 82132 (14.43% of 569221) affected shaders:
Instrs: 26564632 -> 26564913 (+0.00%); split: -0.00%, +0.00%
Cycle count: 4630907475 -> 4631809133 (+0.02%); split: -0.16%, +0.18%
Max live registers: 5425037 -> 5417062 (-0.15%)
Max dispatch width: 128384 -> 132848 (+3.48%); split: +12.92%, -9.45%
LNL fossils-db results :
Totals:
Instrs: 141870413 -> 141870745 (+0.00%); split: -0.00%, +0.00%
Cycle count: 20176018818 -> 20191262632 (+0.08%); split: -0.07%, +0.14%
Max live registers: 44858167 -> 44838370 (-0.04%)
Totals from 51859 (10.55% of 491590) affected shaders:
Instrs: 16834547 -> 16834879 (+0.00%); split: -0.00%, +0.00%
Cycle count: 5761980106 -> 5777223920 (+0.26%); split: -0.24%, +0.50%
Max live registers: 5893878 -> 5874081 (-0.34%)
Perf A/B testing only reported a 0.5% improvement on DG2 on one trace, no changes on BMG.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36958 >
2025-08-26 12:03:22 +00:00
Lionel Landwerlin
27c69acb6a
brw: remove uniform from opt_offsets
...
Those are for push constants, no point in doing that because :
- there is no HW constant offsets in push constants (payload
delivery), it's just register offset calculation
- if we have an dynamic value it's already using MOV_INDIRECT
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: e103afe7bekenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36958 >
2025-08-26 12:03:22 +00:00
Brais Solla
ae7f9552be
r300: Added support for GL_ATI_meminfo and GL_NVX_gpu_memory_info
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36859 >
2025-08-26 11:47:18 +00:00
Danylo Piliaiev
8faf76a754
tu/a6xx: Fix unaligned buffer_to_image on close to (1 << 14) width
...
I'm not sure why exactly it didn't work because
TPL1_A2D_SRC_TEXTURE_SIZE seemingly has (1 << 15) width
limit. However tests have shown that it doesn't work out.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36939 >
2025-08-26 10:56:13 +00:00
Danylo Piliaiev
a288b77403
tu: Fix unaligned image_to_buffer on close to (1 << 14) width
...
The bottom right corner of the copy exceeded the maximum allowed
value in GRAS_A2D_DEST_BR.x
In order to fix this, we have to do a second copy per line of
the last texels.
Fixes asserts in:
dEQP-GLES31.functional.copy_image.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36939 >
2025-08-26 10:56:13 +00:00
Eric Engestrom
2e33098162
docs/ci: always build the docs
...
It only takes 2 min of runner time, and it's been broken several times
by now, so let's just always run this job.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36893 >
2025-08-26 09:49:56 +00:00
Eric Engestrom
a569a5f9c6
docs/ci: drop unnecessary comment
...
None of the other `rules:` say this, because everyone know this by now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36893 >
2025-08-26 09:49:56 +00:00
Eric Engestrom
1b7dd64977
docs/ci: drop redundant/dead fork rule
...
`.common-rules` already covers that.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36893 >
2025-08-26 09:49:55 +00:00
Job Noorman
51fa8ad748
freedreno/drm-shim: disable VM_BIND
...
Turnip crashes under drm-shim when enabling VM_BIND. We don't care about
VM_BIND for shader compilation so just disable it.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Fixes: 4efbfa1441https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37000 >
2025-08-26 09:09:48 +00:00
Eric Engestrom
a033cfaa66
broadcom/ci: add ci-tron variant of the piglit traces job
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854 >
2025-08-26 08:38:10 +00:00
Eric Engestrom
3ce27c08b4
piglit/ci: configure ci-tron to download traces and upload renders
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854 >
2025-08-26 08:38:10 +00:00
Eric Engestrom
137ccdbc54
ci-tron: avoid uploading downloaded traces
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854 >
2025-08-26 08:38:10 +00:00
Eric Engestrom
24f5f5037b
ci-tron: move s3_jwt token file to the project dir
...
CI-tron only passes that folder to the dut, not the rest of the system;
this allows CI-tron jobs to upload things to s3.fd.o, like piglit traces
failed renders.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854 >
2025-08-26 08:38:09 +00:00
Eric Engestrom
9ae98a081b
broadcom/ci: drop unnecessary variables redefinitions
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854 >
2025-08-26 08:38:09 +00:00
Samuel Pitoiset
944e26eae7
radv: fix hashing graphics pipeline when no stages are compiled
...
It's possible with GPL.
This fixes a NULL pointer dereference with updated pipeline binaries
tests in VKCTS.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36999 >
2025-08-26 07:37:40 +00:00
Karol Herbst
b9f060438f
nak: rework scale argument of compute_mat and rename it
...
"scale" was a bad name as it meant nothing others could comprehend.
However that value corresponded to the tile size of the Matrix layouts.
For int8 we have a tile size of 4, for 16 and 32 bit values we have a size
of 2.
For the future the same value need to be 32 for booleans, 8 for int4, 1
for fp64 and tf32 and 4 for all em types.
The "scale = 1 << scale;" assignment can simply be removed because it was
4 for 2 and 2 for 1 simply being the expected value after this change.
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36391 >
2025-08-26 09:06:51 +02:00
Georg Lehmann
d0f4b535fe
nir: constant fold txd with 0 ddx/ddy to txl
...
Foz-DB GFX1201:
Totals from 34 (0.04% of 80287) affected shaders:
Instrs: 3111158 -> 3111076 (-0.00%)
CodeSize: 16345020 -> 16344908 (-0.00%); split: -0.00%, +0.00%
Latency: 15378053 -> 15378063 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 2940485 -> 2940477 (-0.00%); split: -0.00%, +0.00%
VClause: 79940 -> 79941 (+0.00%)
Copies: 228205 -> 228159 (-0.02%)
VALU: 1730040 -> 1729994 (-0.00%)
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36967 >
2025-08-26 06:19:43 +00:00
Arseny Kapoulkine
bb3727ce5a
ac/rgp: Warn when RGP capture can't be saved without libelf
...
Without this, mesa build on some distros may silently produce a version
of radv that silently refuses to save RGP traces
Signed-off-by: Arseny Kapoulkine <arseny.kapoulkine@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36960 >
2025-08-26 00:42:16 +00:00
Mark Collins
098521559d
freedreno/drm: Only initialize memory data source when Perfetto is active
...
FdMemoryDataSource was being registered as a Perfetto data source
unconditionally which led to anything calling fd_device_new(...)
attempting to do this even when they might not have Perfetto
initialized which is done as a part of util_perfetto_init, without
which trying to register the event causes a SEGFAULT.
Fixes: c7045e3e63mark@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36993 >
2025-08-25 22:04:45 +00:00
Connor Abbott
7d925dbc52
freedreno/ci: Update a750 expectations
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533 >
2025-08-25 20:11:58 +00:00
Martin Roukala (né Peres)
44dbf8756e
freedreno/ci: uprev the kernel for the a750
...
We are still in the process of moving our kernels to gfx-ci/linux, but
we got the request to uprev the kernel a month ago when I started my
holiday, so let's not delay it more. Anyway, it is better to change
only one variable at a time so no harm done.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533 >
2025-08-25 20:11:58 +00:00
Connor Abbott
d921225af1
freedreno/ci: Update kernel with VM_BIND fixes
...
Pull in msm-fixes plus a few extra fixes we've accumulated from the
list.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533 >
2025-08-25 20:11:58 +00:00
