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4463 Commits

Author SHA1 Message Date
Rhys Perry 522f135d06 radv: expose VK_KHR_shader_integer_dot_product 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12617>
 2021-09-03 13:21:28 +00:00
Rhys Perry 4dd420f76d radv,aco: implement iadd_sat 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12617>
 2021-09-03 13:21:28 +00:00
Rhys Perry 44be450dc1 radv: refactor handling of nir_options 
Make it easier to change them depending on chip_class and family.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12617>
 2021-09-03 13:21:28 +00:00
Rhys Perry d6619d0a01 ac/llvm,radv: implement uadd_sat/iadd_sat 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12617>
 2021-09-03 13:21:27 +00:00
Samuel Pitoiset ad878856e6 radv/llvm: rework VS input loads and implement the callback 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12693>
 2021-09-03 08:14:51 +00:00
Samuel Pitoiset 1402c17e4f radv: optimize VRS when no depth stencil attachment is bound 
This is allowed by the Vulkan spec and we have to handle this situation
internally. We used to create and bind a 4096x4096 image to copy the
VRS rates but this wasted too much VRAM (~33MiB). Now, the driver only
allocates a HTILE buffer (~1MiB) and bind it to the framebuffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12243>
 2021-09-02 19:39:04 +00:00
Samuel Pitoiset ab635b024b radv: pass the HTILE buffer to radv_copy_vrs_htile() 
Will be used to use a global HTILE buffer without an image.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12243>
 2021-09-02 19:39:04 +00:00
Samuel Pitoiset ad60354a92 radv: optimize copying VRS rates to the global HTILE buffer 
By skipping the read operation which is unnecessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12243>
 2021-09-02 19:39:04 +00:00
Samuel Pitoiset 0fd40af59f radv: allow to conditionally read HTILE value when copying VRS rates 
When a subpass is bound without a VRS attachment, the driver has to
create one internally and the copy can be a write only operation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12243>
 2021-09-02 19:39:04 +00:00
Samuel Pitoiset 607a14b870 radv: remove NGG streamout support in LLVM 
It has never really been used due to various issues with GDS in the
past and it will be lowered in NIR at some point.

The driver support is still there because it can likely be re-used.
This implementation can also be used as a reference point.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12695>
 2021-09-02 17:58:51 +02:00
Samuel Pitoiset b31994cf67 radv: fix determining the maximum number of waves that can use scratch 
This estimation was incorrect, the number of waves doesn't only
depend of the number of VGPRs.
Though, {SPI,COMPUTE}_TMPRING_SIZE.WAVES should limit the number of
scratch waves in flight, not sure if limiting it really works.

This fixes a GPU hang with an upcoming game, and this might also
helps resolving some spurious random GPU hangs.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12700>
 2021-09-02 15:09:07 +00:00
Samuel Pitoiset da9f1a7340 radv: use common vkGet{Buffer,Image}MemoryRequirements() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12416>
 2021-09-02 10:56:39 +00:00
Samuel Pitoiset 48cae114c2 radv: use common vkBind{Buffer,Image}Memory() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12416>
 2021-09-02 10:56:39 +00:00
Samuel Pitoiset 757545b90e radv: use common vkGetDeviceQueue() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12416>
 2021-09-02 10:56:39 +00:00
Samuel Pitoiset 9fc16b66d0 radv: use common vkGetPhysicalDevice{Image}FormatProperties() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12416>
 2021-09-02 10:56:39 +00:00
Samuel Pitoiset 8a9c17bf4e radv: use common entrypoints for sparse image requirements/properties 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12416>
 2021-09-02 10:56:39 +00:00
Samuel Pitoiset e62d3db64b radv: do not disable DCC for storage images if atomics aren't enabled 
VK_FORMAT_R32_SFLOAT seems pretty common and it seems we can be a
little smarter when shader image 32-bit float atomics aren't enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12406>
 2021-09-02 10:40:43 +02:00
Samuel Pitoiset a17756c865 radv: track if shader image 32-bit float atomics are enabled 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12406>
 2021-09-02 10:40:42 +02:00
Samuel Pitoiset 8dd9287ce5 radv: call nir_lower_int64() for LLVM 
Seems to run fine now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12665>
 2021-09-02 08:04:22 +02:00
Samuel Pitoiset 971a373caf radv: use radeon_set_sh_reg_seq() more for initial gfx/compute state 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12671>
 2021-09-01 20:46:29 +00:00
Mike Blumenkrantz 7aef59ccd2 radv: add some asserts for descriptor updating 
let's avoid any further issues with descriptor sizing

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12620>
 2021-09-01 20:08:24 +00:00
Mike Blumenkrantz 34f0aef19b radv: just use UINT64_MAX when getting absolute timeout for that value 
this would otherwise result in (UINT64_MAX - gettime()), which can effectively
be rounded to UINT64_MAX without a noticeable change

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12680>
 2021-09-01 17:47:33 +00:00
Timur Kristóf f4a65e5628 ac/nir/nggc: Only repack arguments that are needed. 
Don't repack everything, only what is actually used.
The goal of this commit is primarily to remove unnecessary
LDS stores and loads. In addition to that, it also gets rid of
a few VALU instructions and reduces VGPR use.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 6951 (5.40% of 128647) affected shaders:
VGPRs: 206056 -> 205360 (-0.34%); split: -0.79%, +0.45%
CodeSize: 12344568 -> 12269312 (-0.61%); split: -0.62%, +0.01%
MaxWaves: 211206 -> 212196 (+0.47%)
Instrs: 2319459 -> 2308483 (-0.47%); split: -0.50%, +0.03%
Latency: 7220829 -> 7164721 (-0.78%); split: -1.21%, +0.43%
InvThroughput: 1051450 -> 1049191 (-0.21%); split: -0.36%, +0.15%
VClause: 25794 -> 25445 (-1.35%); split: -1.97%, +0.61%
SClause: 39192 -> 39277 (+0.22%); split: -0.21%, +0.43%
Copies: 315756 -> 313404 (-0.74%); split: -1.17%, +0.42%
Branches: 127878 -> 127879 (+0.00%); split: -0.00%, +0.00%
PreVGPRs: 168029 -> 160162 (-4.68%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
 2021-09-01 14:45:14 +00:00
Samuel Pitoiset 640f15edd7 radv/llvm: fix invalid IR when converting triangle strips to indices 
Operand 0 of LLVMBuildSelect() should be i1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12616>
 2021-08-31 09:56:27 +02:00
Mike Blumenkrantz 66fa676e8d radv: ignore dynamic line stipple if line stipple isn't enabled 
==244108== Conditional jump or move depends on uninitialised value(s)
==244108==    at 0x48498D5: bcmp (vg_replace_strmem.c:1129)
==244108==    by 0x1C37B7DD: radv_bind_dynamic_state (radv_cmd_buffer.c:237)
==244108==    by 0x1C388027: radv_CmdBindPipeline (radv_cmd_buffer.c:4794)
==244108==    by 0x14E9C01E: bool update_gfx_pipeline<true>(zink_context*, zink_batch_state*, pipe_prim_type) (zink_draw.cpp:406)
==244108==    by 0x14E9AAB9: void zink_draw_vbo<(zink_multidraw)1, (zink_dynamic_state)1, (zink_dynamic_state2)1, (zink_dynamic_vertex_input)1, true>(pipe_cont>
==244108==    by 0x14B017EB: tc_call_draw_single (u_threaded_context.c:3033)
==244108==    by 0x14AF9C0E: tc_batch_execute (u_threaded_context.c:190)
==244108==    by 0x14AFA24F: _tc_sync (u_threaded_context.c:341)
==244108==    by 0x14B006E7: tc_texture_subdata (u_threaded_context.c:2549)
==244108==    by 0x14238F8C: st_TexSubImage (st_cb_texture.c:2134)
==244108==    by 0x14239931: st_TexImage (st_cb_texture.c:2363)
==244108==    by 0x1453698A: teximage (teximage.c:3154)
==244108==    by 0x1453698A: teximage_err (teximage.c:3181)
==244108==    by 0x145388BD: _mesa_TexImage2D (teximage.c:3252)
==244108==    by 0x5E88D4: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5E9527: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5E9B72: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5F1092: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5F10AC: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x48CC66: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x48DDC7: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x40D525: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x4FF7B74: (below main) (in /usr/lib64/libc-2.33.so)
==244108==  Uninitialised value was created by a stack allocation
==244108==    at 0x14ECDF55: zink_create_gfx_pipeline (zink_pipeline.c:53)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12618>
 2021-08-30 19:24:29 +00:00
Mike Blumenkrantz 90a0556c27 radv: use pool stride when copying single query results 
the specified stride is irrelevant for this case since there's only one
result to write

Cc: mesa-stable

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12619>
 2021-08-30 19:02:40 +00:00
Samuel Pitoiset 906f7f4296 radv: advertise VK_EXT_primitive_topology_list_restart 
Everything should be already supported, except patch list.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12611>
 2021-08-30 18:39:20 +00:00
Samuel Pitoiset 2d1b85fe22 radv: add support for clearing multi layers with normal gfx clear path 
Allow to clear range of layers with vkCmdClear{Color,DepthStencil}Image().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12557>
 2021-08-30 16:19:29 +00:00
Samuel Pitoiset 23ef0fb277 radv: do not allocate a clear value for images that support comp-to-single 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12565>
 2021-08-30 07:18:19 +00:00
Samuel Pitoiset df688e6941 radv: do not load/store the clear value for comp-to-single images 
Images that are fast cleared with the comp-to-single mode clears DCC
to 0x10 which tells the hardware to get the clear value from the
main surface instead of the reg.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12565>
 2021-08-30 07:18:19 +00:00
Samuel Pitoiset 0c550a5fe6 radv: disable DCC image stores on Navi12-14 for displayable DCC corruption 
DCC image stores require 128B but 64B is used for displayable DCC.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5265
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5106
Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12521>
 2021-08-30 08:28:37 +02:00
Samuel Pitoiset d90a8c79df radv: remove unecessary radv_finishme() for invalid color formats 
Something really bad happen (likely driver bug) if this is triggered.
Replace with some assertions to catch an eventual issue in debug build.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12556>
 2021-08-27 07:29:17 +00:00
Samuel Pitoiset df90bb3f88 radv: remove useless check about number of samples in the HW resolve path 
Although this can likely hang, this is invalid and should be caught
by the validation layers. There is many ways to hang the GPU with VK,
this check alone is useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12556>
 2021-08-27 07:29:17 +00:00
Samuel Pitoiset b05c2023cc radv: remove outdated radv_finishme() in the HW resolve path 
Resolving layered MSAA images is actually implemented by the HW
resolve path but never used because the driver uses the compute path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12556>
 2021-08-27 07:29:17 +00:00
Timur Kristóf c4ca08548b radv: Remove superfluous workgroup size calculations. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12321>
 2021-08-26 09:46:18 +00:00
Timur Kristóf 9fd36bbacd radv: Calculate workgroup sizes in radv_pipeline. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12321>
 2021-08-26 09:46:18 +00:00
Timur Kristóf 5b7446d74c radv, ac, aco: Use indices 0-2 of gs_vtx_offset argument array on GFX9+. 
Previously, indices 0, 2, 4 were used.
This worked, but it was somewhat unintuitive.
This commit changes it to use indices 0, 1, 2 instead, which
makes the code easier to understand.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12511>
 2021-08-26 05:20:15 +00:00
Samuel Pitoiset 0f05c84bba radv: allow storage images with VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 on GFX10.3+ 
It should be supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12543>
 2021-08-25 16:27:46 +00:00
Daniel Schürmann a3110c308f radv: call nir_lower_flrp() after the first radv_optimize_nir() 
instead of inside the optimization loop

Totals from 2504 (1.67% of 150170) affected shaders: (GFX10.3)
VGPRs: 162592 -> 162416 (-0.11%); split: -0.12%, +0.01%
CodeSize: 18399756 -> 18383552 (-0.09%); split: -0.10%, +0.01%
MaxWaves: 42654 -> 42748 (+0.22%)
Instrs: 3499404 -> 3497075 (-0.07%); split: -0.08%, +0.01%
Latency: 87087238 -> 87064270 (-0.03%); split: -0.06%, +0.03%
InvThroughput: 21159621 -> 21150546 (-0.04%); split: -0.05%, +0.01%
VClause: 56653 -> 56667 (+0.02%); split: -0.00%, +0.03%
Copies: 226332 -> 226423 (+0.04%); split: -0.15%, +0.19%
Branches: 110027 -> 110025 (-0.00%); split: -0.05%, +0.04%
PreSGPRs: 168087 -> 168076 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 160814 -> 160705 (-0.07%)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12061>
 2021-08-24 16:10:30 +00:00
Rhys Perry 94ed2ab3a1 radv: use nir_vector_insert_imm in lower_intrinsics 
This creates a single nir_op_vecn instead of a nir_op_vecn and several
copies.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12469>
 2021-08-24 10:35:19 +00:00
Samuel Pitoiset e0353296da radv: allocate shaders to 32-bit address to skip PGM_HI 
This reduces the number of emitted registers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12466>
 2021-08-23 11:28:21 +00:00
Samuel Pitoiset 2dc90ca8a4 radv: don't use SQ_NON_EVENT before GE_PC_ALLOC for better perf on Navi1x 
Seems it make the perf worse.
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12466>
 2021-08-23 11:28:21 +00:00
Samuel Pitoiset e4e2d45cc6 radv: remove useless DISABLE_{ZMASK,SMEM}_EXPCLEAR_OPTIMIZATION state 
This has no effect without enabling EXPCLEAR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12326>
 2021-08-23 09:52:51 +02:00
Samuel Pitoiset 98d10eed48 radv: remove unused fast depth-stencil gfx clear path with expclear 
This has never been used because it requires to know the previous
clear values which is not really possible in Vulkan.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12326>
 2021-08-23 09:52:48 +02:00
Samuel Pitoiset be6bdb0918 radv: fix copying depth+stencil images on compute 
Using separate aspects is required.

Fixes few CTS failures (dEQP-VK.api.copy_and_blit.*) when the compute
path is forced in the driver. Note that CTS coverage of compute queue
is rather limited.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12287>
 2021-08-20 16:43:22 +00:00
Samuel Pitoiset 067599f8bc radv: remove incorrect comment about compressed writes to HTILE on GFX10+ 
This seems to be unsupported.
COMPRESSION_EN=1 and WRITE_COMPRESS_ENABLE=1 don't update HTILE
with image stores.

Note that there is no issue because depth/stencil images will be
decompressed for image stores, and TC-compat HTILE is disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12450>
 2021-08-20 15:53:32 +00:00
Samuel Pitoiset 1c26751969 radv: remove unnecessary check in radv_layout_is_htile_compressed() 
The driver doesn't enable TC-compat HTILE for storage images, so this
was actually always TRUE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12450>
 2021-08-20 15:53:32 +00:00
Marek Olšák 94d261029e radv: allow arbitrary swizzle modes for displayable DCC 
by adding retile pipeline variants

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430>
 2021-08-20 14:28:36 +00:00
Samuel Pitoiset ab35a63dea radv: do not allocate the FCE predicate for images that use comp-to-single 
Images that support comp-to-single don't have to be fast-cleared at
all, so the predicate is unnecessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12323>
 2021-08-19 07:50:50 +00:00
Samuel Pitoiset ef546cf96f radv: remove useless check about the FCE predicate offset 
radv_update_fce_metadata() already prevents that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12323>
 2021-08-19 07:50:50 +00:00