Commit Graph

169467 Commits

Author SHA1 Message Date
Ian Romanick
aeb8af1141 nir/loop_analyze: Track induction variable basis information
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>
2023-04-06 23:50:27 +00:00
Ian Romanick
30879a760c nir/loop_analyze: Add a function to evaluate an ALU as constant
...with a substitution. This function is largely a copy-and-paste of
try_fold_alu (nir_opt_constant_folding.c), and an argument could be made
that this function belongs in that file.

v2: Some changes were mistakenly squashed in to "nir/loop_analyze: Use
try_eval_const_alu and induction variable basis info" that should have
been here.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>
2023-04-06 23:50:27 +00:00
Ian Romanick
2e942909c8 nir/tests: Add many loop analysis tests for induction variables modified by imul
Loop analysis doesn't currently treat values updated by multiplication
as induction variables. Future patches will change this.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>
2023-04-06 23:50:27 +00:00
Ian Romanick
a210fcd9c7 nir/tests: Add more loop analysis tests for induction vars updated by shifts
These reverse the order of the comparison (e.g., -2 >= i vs i >= -2). I
split this into a separate commit because the previous commit was so
large.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>
2023-04-06 23:50:27 +00:00
Ian Romanick
45518d2eba nir/tests: Add many loop analysis tests for induction vars updated by shifts
Loop analysis doesn't currently treat values updated by shifts as
induction variables. Future patches will change this.

v2: Don't use the contradiction ilt(x, INT_MIN).

v3: Delete some errant code in UNKNOWN_COUNT_TEST. Noticed by Tim.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>
2023-04-06 23:50:27 +00:00
Sajeesh Sidharthan
4f1646d73f radeonsi/vcn: set bitstream buffer size to encoded bitstream size
initial bitstream size was set to width * height * 2 which is
larger than yuv size. set initial bitstream size to encoded
bitstream size approximately to optimize memory consumption.
This is just an initial size setting, it will get resized later
if it's not big enough. As a result of this change, we don't need to
allocate super big size at the every beginning. Only allocate
big size when needed in order to save some memory

Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Acked-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21918>
2023-04-06 22:55:59 +00:00
Jesse Natalie
a3e5e6ceaa dzn: Fix bindless descriptor sets with multiple dynamic buffers that need custom descriptors
Fixes: 5d2b4ee4 ("dzn: Allocate descriptor sets in buffers for bindless mode")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
04fa6c715b dzn: Batch command lists together
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
e16b55d861 dzn: Don't do initial-layout barriers for simultaneous-access resources
Fixes: 4daeac01 ("dzn: Enhanced barriers fixes/workarounds")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
023f7b26dc dzn: Attempt to force depth write states for depth access in LAYOUT_GENERIC
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
c914d53d13 dzn: Ensure buffer offsets are aligned
If the app passes us unaligned buffer offsets, we need to align them
down to the nearest aligned offset, and then put the difference into
the descriptor set buffer.

Fixes: 8bd5fbf8 ("dzn: Bind buffers for bindless descriptor sets")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
eaa8c8097c dzn: Don't use write-combine memory for cache-coherent UMA
Cache coherent UMA implies that the GPU is reading data through the
CPU caches. Using write-combined CPU pages for such a system would
be bad, since the GPU would then be reading uncached data. One
example of such a system is WARP. This significantly improves WARP's
performance for some apps (including the CTS).

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
3db019a816 dzn: Ensure pipeline variants are used for dynamic stencil masks
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
460ee81913 dzn: Align descriptor sets in the bindless buffer
Fixes: 5d2b4ee4 ("dzn: Allocate descriptor sets in buffers for bindless mode")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
84c0f40490 dzn: Report some more caps correctly that are supported
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
a348b49901 dzn: Raise max number of descriptor sets to 8
DOOM Eternal just assumes you support at least 5, which caused corruption
due to overrunning arrays. We can just bump this up. 8 should work with
and without bindless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
f2a5a03d3b dzn: Fix SRV barrier state on compute command lists
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
fb5abb956d dzn: Add a driconf option for enabling subgroup ops in VS/GS
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
89879d8fe2 dzn: Add a driconf entry for enabling 8bit loads and stores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
e28328ca2c spirv2dxil: Add some more supported caps
8-bit loads and stores work via lowering, but they do work

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
6d5ff875d2 microsoft/compiler: Fix large shifts
Unlike DXBC, DXIL's shift instructions don't have the implicit behavior
that they only take the 5 bits. This is observable if you try to have
DXC do a shift of a dynamic value, e.g. a constant buffer value, where
the compiler inserts the appropriate 'and' op. We need to do the same.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
4f56cede6d microsoft/compiler: Assign 1D wave IDs based on local thread ID
Fixes corruption/flickering seen in DOOM Eternal's decals/lighting.
It seems the shader has an implicit assumption about this property.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
eeb67362da microsoft/compiler: Fix barrier for wave ID computation
Fixes: 2f8a8b59 ("microsoft/compiler: Add lowering passes for basic subgroup vars")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Jesse Natalie
477332a347 microsoft/compiler: Fix 8-bit loads and stores when supporting 16-bit DXIL
Shifts should always use 32bit shift values, and when lowering to
masked, we need to use 32-bit atomics. That means that we should also
treat 24bit stores as a single masked op rather than one 16bit unmasked
and one 8bit masked.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
2023-04-06 22:08:28 +00:00
Adam Jackson
e89e1f5049 glx: Fix error handling yet again in CreateContextAttribs
Unlike the legacy CreateContext path, we would try to send the
GLXCreateContextAttribs request regardless of whether we'd successfully
created the client context state. And there's not a lot on the server
side to go wrong besides BadAlloc, so if the request succeeded but
the client side didn't we'd need to destroy the server context and
synthesize an X error. Since that itself involves more X protocol it's
tricky to get the request number right in the error, and tests and apps
can notice when you get it wrong.

Since we have now fixed client-side validation to generate the right
errors at the right times, this patch does something simpler, we match
CreateContext and fail early if the client-side setup fails. Now there's
no question of what request number to use, because we haven't sent any
protocol, the error is for the request as if it'd been sent.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4763
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>
2023-04-06 21:29:54 +00:00
Adam Jackson
86fd72448c glx: Disable the indirect fallback in CreateContextAttribs
If your app cares enough to use CreateContextAttribs it's probably not
going to be happy with the pre-GL-1.5 indirect experience.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>
2023-04-06 21:29:54 +00:00
Adam Jackson
5dba6726f7 glx/dri: Fix error generation for invalid GLX_RENDER_TYPE
This needs to throw BadValue.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>
2023-04-06 21:29:54 +00:00
Adam Jackson
dd67c079a0 dri: Validate more of the context version in validate_context_version
There's two kinds of "bad version" you might encounter here, either the
combination does not name a defined version (like 1.7) or it names
something the driver can't do (like asking r300 to do 4.0). EGL does not
distinguish these cases, but GLX calls them BadMatch and GLXBadFBConfig
respectively.

Since api_mask is the set of driver supported APIs, and we can only
support defined APIs, don't check it early in driCreateContextAttribs,
just let it fall out from validate_context_version.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>
2023-04-06 21:29:54 +00:00
Adam Jackson
9c76682d80 glx/dri: Use X/GLX error codes for our create_context_attribs
This has no functional change because everyone calling this is
discarding the error code, because we're relying on the server to
generate the right thing for us. But we create the direct context first
and the server isn't going to enforce everything we want it to
(supported GL versions for example). Convert out from DRI error codes to
X/GLX error codes so we can fail the right way on the client side. We're
still throwing the error away in all of the callers but that'll change
shortly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>
2023-04-06 21:29:54 +00:00
Ian Romanick
12e11fa3e4 intel/fs: White space fixes
Trivial

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>
2023-04-06 19:07:50 +00:00
Ian Romanick
6dfb7061e0 intel/fs: Preserve meta data more often in brw_nir_move_interpolation_to_top
This pass rarely makes any changes, so work a little harder to preserve
more meta data.

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a debugoptimized build, improves
performance of Vulkan CTS "deqp-vk --deqp-case='dEQP-VK.*spir*'" by
-0.2% ± 0.1% (n = 5, pooled s = 0.431885).

v2: Add some parenthesis. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>
2023-04-06 19:07:50 +00:00
Ian Romanick
3037603b70 intel/fs: Linked list micro optimizations in brw_nir_move_interpolation_to_top
Two linked list management changes:

- Use the list head sentinel as the initial cursor. It is, after all, a
  proper node in the list.

- Iterate the list of blocks starting with the second block instead of
  skipping the first block in the loop.

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a release build, improves
performance of compiling shaders from batman_arkham_city_goty.foz by
-0.24% ± 0.09% (n = 5, pooled s = 0.324106).

v2: Use nir_cursor instead of direct list manipultion. Suggested by
Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>
2023-04-06 19:07:50 +00:00
Ian Romanick
78ee74de4a intel/compiler: Micro optimize regions_overlap
On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a release build, improves
performance of compiling shaders from batman_arkham_city_goty.foz by
-1.09% ± 0.084% (n = 5, pooled s = 0.354471)

Reduces the size of a release build by 26k.

   text	   data	    bss	    dec	    hex	filename
23163641 400720	 231360	23795721	16b1809	before/lib64/dri/iris_dri.so
23137264 400720	 231360	23769344	16ab100	after/lib64/dri/iris_dri.so

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>
2023-04-06 19:07:50 +00:00
Ian Romanick
7873edee6e intel/fs: Use specialized version of regions_overlap in opt_copy_propagation
Since one of the register must always be either VGRF or FIXED_GRF, much
of regions_overlap and reg_offset can be elided.

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a debugoptimized build, improves
performance of Vulkan CTS "deqp-vk --deqp-case='dEQP-VK.*spir*'" by
-0.29% ± 0.097% (n = 5, pooled s = 0.361697).

Using a release build, improves performance of compiling shaders from
batman_arkham_city_goty.foz by -3.3% ± 0.04% (n = 5, pooled s =
0.178312).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>
2023-04-06 19:07:50 +00:00
Ian Romanick
43cb42df7c intel/compiler: Micro optimize inst_is_in_block
This function only exists in builds with assertions, so it only matters
there.

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a debugoptimized build, improves
performance of Vulkan CTS "deqp-vk --deqp-case='dEQP-VK.*spir*'" by
-5.2% ± 0.16% (n = 5, pooled s = 0.657887).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>
2023-04-06 19:07:50 +00:00
Ian Romanick
d47f521ee4 intel/compiler: Use NIR_PASS instead of NIR_PASS_V
Reduce debug log spam by only logging the shader if a pass made some
changes. This can also elide some nir_validate calls in debug builds.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>
2023-04-06 19:07:50 +00:00
Ian Romanick
fb950a9edf intel/compiler: Remove one overload of backend_instruction::insert_before
The version that takes a list of instructions is not used. I did not do
any archaeology to find out when the last user was removed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>
2023-04-06 19:07:50 +00:00
Tomeu Vizoso
179a694232 etnaviv: don't read too much from uniform arrays
Fixes: 77af1ca690 ("etnaviv: add disk cache")
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>
2023-04-06 16:51:36 +00:00
Italo Nicola
c45ce64ea0 etnaviv: implement nir_op_uclz and lower find_{msb,lsb} to uclz
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>
2023-04-06 16:51:36 +00:00
Italo Nicola
9dc4ee9121 etnaviv: lower (un)pack_{2x16,2x32}_split and extract_{byte,word}
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>
2023-04-06 16:51:36 +00:00
Tomeu Vizoso
70bb190279 etnaviv: print writemask of store operations
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>
2023-04-06 16:51:36 +00:00
Tomeu Vizoso
194327c136 etnaviv: handle missing alu conversion opcodes
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>
2023-04-06 16:51:36 +00:00
Italo Nicola
2a111d520e etnaviv: add default clear_buffer and clear_texture APIS
These are required to support rusticl.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>
2023-04-06 16:51:35 +00:00
Italo Nicola
201a141798 etnaviv: use stderr for compiler error logging
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>
2023-04-06 16:51:35 +00:00
Italo Nicola
3b7d35bb99 etnaviv: abort() instead of assert(0) on compiler error
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>
2023-04-06 16:51:35 +00:00
Marek Olšák
debc543904 amd/registers: use gfx9 packet definitions for gfx940
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
2023-04-06 15:00:54 +00:00
Marek Olšák
ba74d10950 amd/registers: update gfx940.json
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
2023-04-06 15:00:54 +00:00
Marek Olšák
e3bc800d5d amd/registers: fix the parser to include CP_COHER registers for gfx940
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
2023-04-06 15:00:54 +00:00
Marek Olšák
e917db3b42 amd/registers: simplify integer division by 0x1000 in the parser
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
2023-04-06 15:00:54 +00:00
Marek Olšák
81a6601979 radeonsi: don't set registers that don't exist on gfx940
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
2023-04-06 15:00:53 +00:00