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dzn: Don't use write-combine memory for cache-coherent UMA

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Cache coherent UMA implies that the GPU is reading data through the
CPU caches. Using write-combined CPU pages for such a system would
be bad, since the GPU would then be reading uncached data. One
example of such a system is WARP. This significantly improves WARP's
performance for some apps (including the CTS).

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>
This commit is contained in:
Jesse Natalie
2023-03-27 11:09:57 -07:00
committed by Marge Bot
parent 3db019a816
commit eaa8c8097c
1 changed files with 2 additions and 1 deletions
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src/microsoft/vulkan/dzn_device.c
+2 -1
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@@ -2596,7 +2596,8 @@ dzn_device_memory_create(struct dzn_device *device,
((mem_type->propertyFlags & VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) &&
!pdevice->architecture.UMA) ?
D3D12_MEMORY_POOL_L1 : D3D12_MEMORY_POOL_L0;
if (mem_type->propertyFlags & VK_MEMORY_PROPERTY_HOST_CACHED_BIT) {
if ((mem_type->propertyFlags & VK_MEMORY_PROPERTY_HOST_CACHED_BIT) ||
((mem_type->propertyFlags & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT) && pdevice->architecture.CacheCoherentUMA)) {
heap_desc.Properties.CPUPageProperty = D3D12_CPU_PAGE_PROPERTY_WRITE_BACK;
} else if (mem_type->propertyFlags & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT) {
heap_desc.Properties.CPUPageProperty = D3D12_CPU_PAGE_PROPERTY_WRITE_COMBINE;