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Author SHA1 Message Date
Jordan Justen abace2b8a4 iris: Align buffer VMA to 2MiB for XeHP 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14155>
 2021-12-13 22:29:18 +00:00
Jordan Justen c17e2216dd anv: Align buffer VMA to 2MiB for XeHP 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14155>
 2021-12-13 22:29:18 +00:00
Jordan Justen f94ff2cc03 iris: Not all gfx12+ have aux_map_ctx 
This code matches other similar cases in iris.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14152>
 2021-12-13 13:30:48 -08:00
Jesse Natalie 36425c43c9 glapi: Never use dllimport/dllexport for TLS vars on Windows 
Fixes: c691149f ("win32: Fixes thread local on win32 with clang/mingw")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14162>
 2021-12-13 16:56:06 +00:00
Rhys Perry 15a375b4c8 radv,aco: don't lower some ffma instructions 
GFX10.3 has no v_mad_f32 and we can't recombine exact ffma into a
v_fma_f32 if they're split. GFX9+ only has v_fma_f16 and no generation has
a 64-bit MAD.

fossil-db (GFX10.3):
Totals from 84040 (57.46% of 146267) affected shaders:
VGPRs: 3717256 -> 3688064 (-0.79%); split: -0.87%, +0.08%
SpillSGPRs: 10419 -> 10403 (-0.15%)
CodeSize: 263064884 -> 262442820 (-0.24%); split: -0.31%, +0.07%
MaxWaves: 2036908 -> 2038374 (+0.07%); split: +0.10%, -0.03%
Instrs: 49849448 -> 49572182 (-0.56%); split: -0.60%, +0.04%
Latency: 908130602 -> 907764246 (-0.04%); split: -0.18%, +0.14%
InvThroughput: 207051300 -> 206762704 (-0.14%); split: -0.24%, +0.10%

fossil-db (GFX10):
Totals from 2 (0.00% of 146267) affected shaders:
Latency: 8123 -> 8107 (-0.20%)

fossil-db (GFX9):
Totals from 2 (0.00% of 146401) affected shaders:
(no statistics affected)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>
 2021-12-13 11:22:33 +00:00
Rhys Perry 165ca5088b radv,aco: implement nir_op_ffma 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>
 2021-12-13 11:22:33 +00:00
Rhys Perry c5f02a1cd3 aco: swap multiplication operands if needed to create v_fmac_f32/etc 
For v_pk_fma_f32 and v_fma_f32 from nir_op_ffma, we don't try to put
scalars in the first operand.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>
 2021-12-13 11:22:33 +00:00
Rhys Perry f4f5d577fc aco: swap operands if necessary to create v_madak/v_fmaak 
Also rewrite the check_literal logic to be more straightforward.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>
 2021-12-13 11:22:33 +00:00
Rhys Perry 2665320c78 aco: create v_fmamk_f32/v_fmaak_f32 from nir_op_ffma 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>
 2021-12-13 11:22:33 +00:00
Rhys Perry a487747ebd aco: use more predictable tiebreaker when forming MADs 
fossil-db (GFX10.3):
Totals from 84981 (58.10% of 146267) affected shaders:
VGPRs: 3829896 -> 3820480 (-0.25%); split: -0.33%, +0.08%
CodeSize: 270860472 -> 270850132 (-0.00%); split: -0.08%, +0.08%
MaxWaves: 2035822 -> 2042516 (+0.33%); split: +0.39%, -0.06%
Instrs: 51285526 -> 51308869 (+0.05%); split: -0.03%, +0.08%
Latency: 931503706 -> 932556231 (+0.11%); split: -0.19%, +0.30%
InvThroughput: 217084232 -> 217070849 (-0.01%); split: -0.12%, +0.11%

fossil-db (GFX10):
Totals from 85520 (58.47% of 146267) affected shaders:
VGPRs: 3729132 -> 3725344 (-0.10%); split: -0.21%, +0.10%
CodeSize: 272796500 -> 272783084 (-0.00%); split: -0.09%, +0.08%
MaxWaves: 2246410 -> 2249012 (+0.12%); split: +0.17%, -0.05%
Instrs: 51643962 -> 51664865 (+0.04%); split: -0.04%, +0.08%
Latency: 932331949 -> 933274979 (+0.10%); split: -0.19%, +0.29%
InvThroughput: 214187040 -> 214130994 (-0.03%); split: -0.13%, +0.11%

fossil-db (GFX9):
Totals from 84619 (57.80% of 146401) affected shaders:
SGPRs: 5366240 -> 5366944 (+0.01%); split: -0.09%, +0.10%
VGPRs: 3765608 -> 3764972 (-0.02%); split: -0.23%, +0.22%
CodeSize: 263634732 -> 263616320 (-0.01%); split: -0.08%, +0.08%
MaxWaves: 546617 -> 547091 (+0.09%); split: +0.18%, -0.09%
Instrs: 51426195 -> 51458334 (+0.06%); split: -0.03%, +0.10%
Latency: 1164445660 -> 1161923480 (-0.22%); split: -0.46%, +0.24%
InvThroughput: 542964697 -> 542329595 (-0.12%); split: -0.26%, +0.14%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>
 2021-12-13 11:22:33 +00:00
Samuel Pitoiset 9a388beda7 radv: ignore dynamic inheritance if the render pass isn't NULL 
From the Vulkan spec:

    "If the pNext chain of VkCommandBufferInheritanceInfo includes a
     VkCommandBufferInheritanceRenderingInfoKHR structure, then that
     structure controls parameters of dynamic render pass instances
     that the VkCommandBuffer can be executed within. If
     VkCommandBufferInheritanceInfo::renderPass is not VK_NULL_HANDLE,
     or VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT is not
     specified in VkCommandBufferBeginInfo::flags, parameters of this
     structure are ignored."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14109>
 2021-12-13 10:48:44 +00:00
Samuel Pitoiset 841949e50b radv: fix dynamic rendering inheritance if the subpass index isn't 0 
The driver will always create only one subpass in the render pass
for inheritance but the subpass index isn't always zero.

This fixes dEQP-VK.multiview.dynamic_rendering.secondary_cmd_buffer*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14109>
 2021-12-13 10:48:44 +00:00
Samuel Pitoiset 43022ecc3a radv: enable lower_lod_zero_width 
This fixes dEQP-VK.glsl.texture_functions.query.texturequerylod.*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14147>
 2021-12-13 10:00:07 +00:00
Samuel Pitoiset be53b3d1bf nir/lower_tex: add lower_lod_zero_width 
On AMD, the hardware will return 0 for the raw LOD if the sum of the
absolute values of derivatives is 0 but Vulkan expects the value to
be in the [-inf, -22.0f] range.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14147>
 2021-12-13 10:00:07 +00:00
Pierre-Eric Pelloux-Prayer 51e772586c radeonsi: use max_zplanes after the last write 
Fixes: c0f723ce2b ("radeonsi: allow and finish TC-compatible MSAA HTILE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>
 2021-12-13 09:13:46 +00:00
Pierre-Eric Pelloux-Prayer 84fea554e3 radeonsi: silence a warning 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>
 2021-12-13 09:13:46 +00:00
Pierre-Eric Pelloux-Prayer 573d645133 radeonsi: fix fast clear / depth decompression corruption 
Insert a flush after a depth decompression pass if the texture
was fast cleared.
This fixes a corruption which seems to only affect gfx10.3 chips.

Ideally we should also clear tex->need_flush_after_depth_decompression
after a flush but there's no easy way for this so this commit will
introduce extra flushes.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>
 2021-12-13 09:13:46 +00:00
Marcin Ślusarz 87f03b1662 nir: limit lower_clip_cull_distance_arrays input to traditional stages 
Compute, task, mesh & raytracing stages don't support
ClipDistance/CullDistance as input.

This change is not needed for correctness. Just something I stumbled on.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14149>
 2021-12-13 08:32:23 +00:00
Roman Stratiienko fcfc4ddfcc v3dv: Fix V3DV_HAS_SURFACE preprocessor condition 
Currently V3DV_HAS_SURFACE is always defined.
There is no WSI for Android in mesa3d, therefore WSI related extensions
should not be exposed.

1. Define V3DV_HAS_SURFACE only for platforms which has WSI implemented.
2. Rename V3DV_HAS_SURFACE -> V3DV_USE_WSI_PLATFORM to align naming
with other platforms.

Fixes dEQP-VK.wsi.android.surface#query_protected_capabilities

Fixes: 79e4451430 ("v3dv: move extensions table to v3dv_device")
Signed-off-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14144>
 2021-12-13 07:11:20 +00:00
Caio Oliveira 2ad11b39bd intel/compiler: Use a struct for brw_compile_bs parameters 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>
 2021-12-13 01:08:16 +00:00
Caio Oliveira 58c4a95320 intel/compiler: Use a struct for brw_compile_gs parameters 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>
 2021-12-13 01:08:16 +00:00
Caio Oliveira acf2d3c78b intel/compiler: Use a struct for brw_compile_tes parameters 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>
 2021-12-13 01:08:16 +00:00
Caio Oliveira 7372a48a4a intel/compiler: Use a struct for brw_compile_tcs parameters 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>
 2021-12-13 01:08:16 +00:00
Dave Airlie 76da456954 crocus: cleanup bo exports for external objects 
This might have led to a leak in firefox/webrender/webgl scenarios

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: f3630548f1 ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14167>
 2021-12-13 10:31:12 +10:00
Marek Olšák 9ff086052a radeonsi: unroll loops of up to 128 iterations 
It's not exactly 128 because longer loop bodies scale the number down.

This improves perf for VP13/Creo and Piano. Most other tests either didn't
show any difference or are CPU-bound.

v2:
- The lowering passes had to be moved to the optimization loop because unrolling creates lowerable variables.
- Piano has some pattern that looks like corruption and the pattern changed with loop unrolling.
  The pattern is present on other drivers as well.

v3:
- I removed the Piano test from CI traces because the image is random. The output was wrong even before
  this MR, and now it's randomly wrong.

|   PERCENTAGE DELTAS    |  Shaders |    SGPRs |    VGPRs |SpillSGPR |SpillVGPR | PrivVGPR |  Scratch | CodeSize | MaxWaves |
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| alien_isolation        |      2936|    .     |    0.02 %|    .     |    .     |    .     |    .     |    0.83 %|    .     |
| deadcore               |        76|   18.47 %|    .     |    .     |    .     |    .     |    .     |  167.69 %|    .     |
| deus_ex_mankind_div..  |      1410|    0.10 %|    0.15 %|    .     |    .     |    .     |    .     |    1.70 %|    .     |
| f1-2015                |       775|    0.37 %|    0.16 %|    .     |    .     |    .     |    .     |    3.25 %|   -0.07 %|
| hitman                 |      1413|    0.10 %|   -0.03 %|    6.45 %|    .     |    .     |    .     |    0.61 %|    0.03 %|
| metro_2033_redux       |      2670|    .     |    .     |    .     |    .     |    .     |    .     |    0.13 %|    0.01 %|
| pixmark-piano-0.7.0    |         2|    .     |   14.29 %| -100.00 %|    .     |    .     |    .     |   78.07 %|   -4.76 %|
| reflections_subway     |        98|   -0.53 %|    .     |    .     |    .     |    .     |    .     |    7.64 %|    .     |
| thea                   |       172|    0.12 %|   -0.81 %|    .     |    .     |    .     |    .     |    0.65 %|    0.15 %|
| ubershaders            |        54|    .     |    .     |    .     |    .     |    .     |    .     |   61.13 %|    .     |
| ue4_effects_cave       |       290|    0.05 %|    .     |    .     |    .     |    .     |    .     |    2.62 %|    .     |
| vp13-creo              |        26|   -3.38 %|   -4.20 %|    .     |    .     |    .     |    .     |   88.56 %|    2.62 %|
| vp13-sw                |       100|   -0.36 %|   -9.14 %|    .     | -100.00 %|    .     | -100.00 %|  -17.97 %|    0.39 %|
| vp20-creo              |        22|   -0.82 %|   -3.33 %|    .     |    .     |    .     |    .     |   81.59 %|    1.51 %|
| vp20-sw                |       296|   -4.51 %|   -0.63 %|    .     |    .     |    .     |    .     |   58.93 %|    0.20 %|
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| All affected           |       189|    3.05 %|   -2.87 %|  500.00 %| -100.00 %|    .     | -100.00 %|  135.61 %|    1.32 %|
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| Total                  |     57794|    0.01 %|   -0.02 %|    0.27 %|   -3.13 %|    .     |   -2.89 %|    1.73 %|    .     |

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Marek Olšák af9ec3c45d radeonsi: add shader profiles that disable binning 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Marek Olšák 4fd8171f64 radeonsi: print more stats for shader-db 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Marek Olšák b3b2f97f2e radeonsi: add Wave32 heuristics and shader profiles 
This generally works well.

There are new cases that select Wave32, and there are shader profiles
which adjust that.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Marek Olšák e2a1883337 glsl: fix setting compiled_source_sha1 without a shader cache 
We need to set it even if Cache == NULL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Marek Olšák 2785141c16 nir: add nir_has_divergent_loop function 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Marek Olšák 26b522eae5 nir: serialize divergent fields 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Marek Olšák 6eb3fe2d4f nir: disable a NIR test due to undebuggable & locally unreproducible CI failures 
debian-vulkan but not any other CI pipeline consistently fails with:
    FileNotFoundError: [Errno 2] No such file or directory: 'nir_tests.xml'

I have to assume that either debian-vulkan is broken, or the NIR test
infrastructure is broken. That's not all. I got the same failure when
I wanted to add a new test, which means the CI is preventing us from adding
new NIR tests, which is a very serious problem with the CI or NIR tests.
The python error doesn't imply that it's a test failure, so something else
is broken. If you don't want such commits to happen again, print better
error messages.

See also the discussion in the MR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Marek Olšák 2ab310b78b nir: handle more intrinsics in divergence analysis 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
 2021-12-11 20:07:35 +00:00
Italo Nicola f0eb163ae0 drisw: do an MSAA resolve when copying the backbuffer 
When calling glXCopySubBuffer, we must resolve the backbuffer before
copying it the frontbuffer.

Fixes piglit's glx/glx-copy-sub-buffer on virgl.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>
 2021-12-11 17:49:00 +00:00
Italo Nicola 6740f34568 virgl: flush cmd buffer when flushing frontbuffer 
When a resource is multisampled, we usually submit a multisampling
resolving blit before we present it or use it in some other way, but
currently we don't always flush the cmd buffer before flushing the
frontbuffer, this commit fixes that.

Fixes piglit's glx/glx-copy-sub-buffer MSAA cases on vtest, in
conjunction with other commits of this series.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>
 2021-12-11 17:49:00 +00:00
Italo Nicola 0577a142de virgl/vtest: implement resource_create_front 
This is required for glXCopySubBufferMESA to work.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>
 2021-12-11 17:49:00 +00:00
Italo Nicola b6d0447027 virgl/vtest: use correct resource stride in flush_frontbuffer 
The displaytarget's resource stride is alignment is currently 64-bytes,
where the shared resource stride is unaligned.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>
 2021-12-11 17:49:00 +00:00
Caio Oliveira a235e02787 util: Use ralloc for strings in cache test 
Also avoid warnings about asprintf result not being checked.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14054>
 2021-12-11 08:06:10 +00:00
Caio Oliveira 51351760c2 util: Convert cache test to use gtest 
Replace a bunch of helper functions for checking results with ones
from GTest.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14054>
 2021-12-11 08:06:10 +00:00
Jason Ekstrand 88e97d75d0 intel/dev: Add gtt_size to devinfo 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13647>
 2021-12-11 05:05:19 +00:00
Jason Ekstrand 1f559930b6 anv: Stop doing too much per-sample shading 
We were setting anv_pipeline::sample_shading_enable based on
sampleShadingEnable without looking at minSampleShading.  We would then
pass this value into nir_lower_wpos_center which would add sample_pos to
frag_coord.  Then the back-end compiler picks up on the existence of
sample_pos and forces persample dispatch.  This leads to doing
per-sample dispatch whenever sampleShadingEnable = VK_TRUE regardless of
the value of minSampleShading.  This is almost certainly costing us
perf somewhere.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14022>
 2021-12-11 04:40:20 +00:00
Nanley Chery 5197809302 iris: Update the initial CCS state on XeHP 
We can't map the CCS on this platform to initialize it into the
PASS_THROUGH state. This can cause issues with optimizations in the
driver that rely on this state.

For example, after rendering to a surface with AUX_NONE, we can then
render to it with AUX_CCS_E without an ambiguate in between (if the CCS
in the PASS_THROUGH state). If that state was incorrect and the aux was
actually compressed, there can be rendering corruption because the
contents may be misinterpreted on the second render.

Use a more accurate initial aux state to avoid these issues.

One notable change in behavior here is that aux surfaces can be created
with fast-cleared blocks even though the caller may specify a modifier
that doesn't support fast clears. This should be fine, so long as all HW
units that can access these surfaces can handle that bit-pattern. We
haven't seen an applicable restriction yet.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Nanley Chery eef4399afd iris: Modify the comment about zeroing CCS 
Among other changes, we highlight the fact that we'll map the CCS -
something we can't do on XeHP.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Nanley Chery cba6d6cad3 iris: Don't assert a NULL aux BO during aux config 
The assert was introduced in a function that allocated an auxiliary
surface BO, iris_resource_alloc_aux. After refactors, the function it's
in now, iris_resource_configure_aux, no longer does this allocation.
Drop the assert because its purpose is unclear and it's no longer
relevant for CCS on XeHP.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Nanley Chery 7d3200a37d iris: Don't allocate and initialize CCS on XeHP 
The memory for CCS on XeHP can't be mapped by the CPU.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Nanley Chery 656d34a811 iris: Drop row pitch param from iris_get_ccs_surf 
This parameter won't be used for XeHP, because we can't directly control
the row pitch of the CCS independently from the main surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Nanley Chery 7d57c9959e iris: Don't allocate a clear color BO for some Z/S 
The only depth/stencil aux usage that can actually use the BO is
ISL_AUX_USAGE_HIZ_CCS_WT. Even with that aux usage, iris may disable
sampling depending on the surface configuration.

Allocate the clear color BO when it'd be usable, not just when the
auxiliary surface size is non-zero on ICL+. This prepares for CCS on
XeHP, which won't have an auxiliary surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Nanley Chery fecd6ae38e iris: Simplify iris_get_aux_clear_color_state_size 
isl_dev.ss.clear_color_state_size is already zero on BDW and SKL. Drop
the redundant platform check and return the field directly.

We're going to have this function return zero more often and it will do
so uniformly using if-statements. We choose to remove the redundant
expression instead of adding a redundant if-statement.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Nanley Chery 4027337004 iris: Move some BO setup to iris_resource_init_aux_buf 
To ease verification, place the assignment and reference of the aux BO
right before the same operations are done for the clear color BO. Also,
move the call to map_aux_addresses that's in the same if-block.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Nanley Chery 9acf0316ec iris: Use the aux BO and surf less during init 
res->aux.bo and res->aux.surf will be NULL and zeroed, respectively, for
CCS on XeHP. Move and modify iris_resource_init_aux_buf to support this.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00