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395 Commits

Author SHA1 Message Date
Nanley Chery
af40104e7d intel: Add underscores to HALIGN and VALIGN enums 
The HALIGN enums for XeHP already have underscores. Make the other
HALIGN and VALIGN enums conform.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery
3d1f6342c0 intel: Update surface states for XeHP alignments 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery
79ad9cda48 intel: Support Tile4/64 in surface states 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery
dd9ae2dc7b intel: Support Tile4/64 in depth/stencil state 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Marcin Ślusarz
4f4f3b1072 genxml: add INSTDONE_GEOM register for Gfx12.5 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12392>
 2021-08-17 08:05:45 +00:00
Lionel Landwerlin
bee7bff48e genxml: add more INSTDONE registers for Gfx12.5 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12392>
 2021-08-17 08:05:45 +00:00
Eric Engestrom
4d9acfa533 python: drop explicit output_encoding='utf-8' in mako templates 
Python 3 handles unicode strings by default, so we can drop all that.

Suggested-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674>
 2021-08-14 21:44:32 +00:00
Eric Engestrom
f1eae2f8bb python: drop python2 support 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674>
 2021-08-14 21:44:32 +00:00
Dave Airlie
de625dddee intel/genxml: fix raster operation field in blt genxml 
This field should be a uint, further changes on top of previous
ones in this area

Fixes: 4d80ec8fcf ("intel/genxml: fix raster op fields on gen4/5")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12164>
 2021-08-03 05:38:25 +10:00
Sagar Ghuge
5ed5d08141 genxml/gen125: Update debug register fields according to HW 
Updating fields helps to decode the error state correctly.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12133>
 2021-08-02 16:45:31 +00:00
Sagar Ghuge
910d5f1973 genxml/gen12: Update debug register fields according to HW 
Updating fields helps to decode the error state correctly.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12133>
 2021-08-02 16:45:31 +00:00
Iván Briano
004fcfe698 anv: fix some multisample lines_wide CTS tests 
We can use a better algorithm from ICL and onward by setting a chicken
bit, but prior to that we need to resort to disabling rectangular lines.
Since we don't support strictLines anyway, this shouldn't be a major
issue.

Closes #2833
Fixes dEQP-VK.rasterization.interpolation_multisample_*_bit.*lines_wide

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11672>
 2021-07-15 17:07:35 +00:00
Jason Ekstrand
63e80d441a intel/genxml: Remove old scratch fields on GFX version 12.5 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
 2021-06-25 00:18:29 +00:00
Jason Ekstrand
8ca0513eca intel/genxml: Add new ScratchSpaceBuffer fields on GFX version 12.5 
Rework:
 * Jordan: Fix MEMZONE_BINDER_START detection
 * Jordan: Bump the IRIS_BINDLESS_SIZE to 8M

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
 2021-06-25 00:18:29 +00:00
Jason Ekstrand
443627fcc0 intel/genxml: Add SURFTYPE_SCRATCH on GFX version 12.5 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
 2021-06-25 00:18:29 +00:00
Dave Airlie
0acd202858 intel/genxml: fix gfx6 GS SVB_INDEX encoding 
This seems to match what the docs + 965 traces say

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>
 2021-06-24 06:50:49 +00:00
Jordan Justen
eb98171252 intel/gen125.xml: Drop GPGPU_WALKER 
Ref: f4902bb189 ("intel/genxml,anv,iris: Drop the legacy compute path from gen125.xml")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11489>
 2021-06-21 19:40:14 +00:00
Dave Airlie
4d80ec8fcf intel/genxml: fix raster op fields on gen4/5 
These should be unsigned integers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Dave Airlie
e5169714ea intel/gemxml: move blitter command to render on gen4/5 
The blitter commands don't show up in INTEL_DEBUG=bat, but on
gen4/5 they are emitted on the render engine ring so just change
the XML to reflect that.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Dave Airlie
c6f34e9fda intel/genxml: rewrite the prefilterop xml to be more consistent. 
This uses a prefix at Ken's suggestion and aligns it across gens

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Dave Airlie
04ed882046 intel/genxml: align gen4/5 xml for store data immediate 
Just align with the gen6 and later xml

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Lionel Landwerlin
b1622af394 intel/genxml: Add coarse pixel shading instructions 
v2: Add Gen12.5

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Anuj Phogat
12099d51f6 intel: Rename gen_10 to ver_10 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
 2021-04-20 20:06:34 +00:00
Anuj Phogat
61e8636557 intel: Rename gen_device prefix to intel_device 
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device/intel_device/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
 2021-04-20 20:06:33 +00:00
Anuj Phogat
cd39d3b1ad intel: Rename gen_device prefix in filenames 
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
find $SEARCH_PATH -type f -name "gen_device" -exec sh -c 'f="{}"; mv -- "$f" "${f/gen_device/intel_device}"' \;
grep -E "gen_device_info*\.[cph]" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device_info\(.*\.[cph]\)/intel_device_info\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
 2021-04-20 20:06:33 +00:00
Felix DeGrood
ed94528711 intel: add L3 Bypass Disable to gen xml 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
 2021-04-15 04:54:40 +00:00
Anuj Phogat
e7e55af4d6 intel: Rename GENx keyword to GFXx 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\([[:digit:]]\+\)/GFX\1/g"

Exclude the changes to modifiers:
grep -E "I915_.*GFX" -rIl $SEARCH_PATH | xargs sed -ie "s/\(I915_.*\)GFX/\1GEN/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat
1d296484b4 intel: Rename Genx keyword to Gfxx 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "Gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/Gen\([[:digit:]]\+\)/Gfx\1/g"

Exclude changes in src/intel/perf/oa-*.xml:
find src/intel/perf -type f \( -name "*.xml" \) | xargs sed -ie "s/Gfx/Gen/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat
b75f095bc7 intel: Rename genx keyword to gfxx in source files 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g"

Exclude pack.h and xml changes in this patch:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
grep -E "gfx[[:digit:]]+\.xml" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat
c1f3a778de intel: Rename GENx prefix in macros to GFXx in source files 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN" -rIl src/intel/genxml | grep -E ".*py" |  xargs sed -ie "s/GEN\([%{]\)/GFX\1/g"
grep -E "[^_]GEN[[:digit:]]+" -rIl $SEARCH_PATH | grep -E ".*(\.c|\.h|\.y|\.l)" | xargs sed -ie "s/\([^_]\)GEN\([[:digit:]]\+\)/\1GFX\2/g"

Leave out renaming GFX12_CCS_E macros. They fall under renaming pattern like "_GEN[[:digit:]]+":
grep -E "GFX12_CCS_E" -rIl $SEARCH_PATH | xargs sed -ie "s/GFX12_CCS_E/GEN12_CCS_E/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat
99331f6deb intel: Rename genx10 field in gen_device_info struct to verx10 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)genx10" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)genx10/info\1\2verx10/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat
9da8a55b08 intel: Rename GEN_GEN macro to GFX_VER 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_GEN/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:06 +00:00
Anuj Phogat
295bb3c263 intel: Rename GEN_VERSIONx10 macro to GFX_VERx10 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_VERSION" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_VERSION/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:06 +00:00
Jason Ekstrand
79d9c914ae intel/genxml: Make BindingTablePoolEnable a bool 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:46:50 -05:00
Jason Ekstrand
65077cdf57 intel/genxml: Binding table pointers are 15 bits on GFX version 12.5+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:33:16 -05:00
Kenneth Graunke
6fb93465bd intel/genxml: Add a partial GT_MODE definition for Gen11+. 
I chose to drop "HW" from the name of this field because on Gen11
it applies to both HW and SW binding tables, so it's a bit of a
misnomer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:32:55 -05:00
Jordan Justen
16d453da7f genxml/gen12: 3D_MODE bits 31:16 are no longer must-be-one 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>
 2021-03-19 09:07:37 +00:00
Anuj Phogat
e66e8a0109 intel: Remove GEN_IS_G4X macro 
GEN_GEN and GEN_VERSIONx10 macros provide a consistent way to do platform
version checks. We can avoid platform specific macros.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
 2021-03-16 16:40:12 +00:00
Anuj Phogat
1d0295ea2c intel: Simplify version checks involving haswell 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
 2021-03-16 16:40:12 +00:00
Anuj Phogat
97d6ceaf04 intel: Remove GEN_IS_HASWELL macro 
Use GEN_VERSIONx10 == 75 check in place of GEN_IS_HASWELL macro.
GEN_GEN and GEN_VERSIONx10 macros provide a consistent way to do platform
version checks. We can avoid platform specific macros.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
 2021-03-16 16:40:12 +00:00
Jason Ekstrand
ee395df315 genxml: Make 1-bit L3$ config register fields bool on Gen7 
Otherwise, they look like booleans but, if you put a value other than
0/1 in them, the GenXML generator code will explode.

Fixes: b6875b0094 "anv: Drop has_slm in emit_l3_config for gen11+"
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9614>
 2021-03-15 17:22:49 -07:00
Jason Ekstrand
5f192b190f anv,genxml: Handle L3SQCREG1_SQGHPCI in GenXML 
Technically, this is only one field on IVB but it's two on BYT and so it
makes things easier if we split it for all Gen7.

While we're here, make some of the other fields in L3SQCREG1 Booleans.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9537>
 2021-03-12 04:17:39 +00:00
Anuj Phogat
692472a376 intel: Rename "gen_" prefix used in common code to "intel_" 
This patch renames functions, structures, enums etc. with "gen_"
prefix defined in common code.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
 2021-03-10 22:23:51 +00:00
Jason Ekstrand
6721925220 genxml: Clean up MI_SET_PREDICATE 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
 2021-03-08 10:47:19 -06:00
Jason Ekstrand
c7c524337a intel/mi_builder: Add load/store_offest on GFX 12.5+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
 2021-03-08 10:47:18 -06:00
Sagar Ghuge
04d0d4e849 intel/mi_builder: Added support for command streamer shift operations 
Add logical shift left and right operations support to mi_builder.

v1:
- Add GEN_GEN > 12 check (Jordan Justen)
- Add gen_mi_has_shift function (Jordan Justen)
- Fix commit title (Jordan Justen)

v2 (Jason Ekstrand):
- Add _imm versions of all of them
- Better handle corner-cases in _imm helpers
- Handle the power-of-two limitation for _imm versions
- Add tests

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
 2021-03-08 10:45:42 -06:00
Jordan Justen
18bc7d9d3f intel: Use devinfo genx10 field 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9329>
 2021-03-01 22:00:08 -08:00
Jordan Justen
36dd7c44f6 intel: Use GEN_VERSIONx10 in more places 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9329>
 2021-03-01 22:00:08 -08:00
Francisco Jerez
ab076e19ed intel/genxml: Define 3DSTATE_SUBSLICE_HASH_TABLE command for Gen12 and Gen12.5. 
This command allows programming custom pixel hashing tables
controlling the balancing of load across pixel pipes.  Rather
confusingly 3DSTATE_SLICE_TABLE_STATE_POINTERS was serving the same
purpose on Gen11: A pixel is mapped to the pixel pipe with index
specified by the entry in the table corresponding to the LSBs of the
pixel coordinates [Yes you read right the entries are neither subslice
nor slice indices!].  Either a 2-way or a 3-way table can be
programmed based on whether the platform has two or three pixel pipes
per slice.  In addition the 16x8 tables defined below can hold two
separate 8x8 tables when in DUAL_TABLE mode (which AFAIA is only
useful for platforms with multiple asymmetric slices -- I.e. no
production platforms as of today to my knowledge).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8749>
 2021-02-23 21:14:57 -08:00
Francisco Jerez
a2a17bf25e intel/genxml: Fix pixel hashing 3DSTATE_3D_MODE field definitions for Gen12 and Gen12.5. 
The former "Subslice Hashing Mode" field is no longer used by the
hardware, Gen12 parts always do 16x16 subslice pixel hashing -- Remove
it since it's no longer useful.  In addition add a couple of bits that
will be useful in order to make some adjustments to the default pixel
pipe hashing behavior.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8749>
 2021-02-23 21:14:42 -08:00