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genxml/gen12: 3D_MODE bits 31:16 are no longer must-be-one

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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>
This commit is contained in:
Jordan Justen
2021-03-10 09:54:15 -08:00
committed by Marge Bot
parent b9a7f9314b
commit 16d453da7f
4 changed files with 10 additions and 2 deletions
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src/gallium/drivers/iris/iris_state.c
+1
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@@ -915,6 +915,7 @@ gen12_upload_pixel_hashing_tables(struct iris_batch *batch)
iris_emit_cmd(batch, GENX(3DSTATE_3D_MODE), p) {
p.SubsliceHashingTableEnable = true;
p.SubsliceHashingTableEnableMask = true;
}
}
#endif
src/intel/genxml/gen12.xml
+4 -1
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@@ -1281,7 +1281,10 @@
<field name="3D Scoreboard Hashing Mode" start="36" end="36" type="bool"/>
<field name="Subslice Hashing Table Enable" start="37" end="37" type="bool"/>
<field name="Slice Hashing Table Enable" start="38" end="38" type="bool"/>
<field name="Mask" start="48" end="63" type="mbo"/>
<field name="Cross Slice Hashing Mode Mask" start="48" end="49" type="uint"/>
<field name="3D Scoreboard Hashing Mode Mask" start="52" end="52" type="bool"/>
<field name="Subslice Hashing Table Enable Mask" start="53" end="53" type="bool"/>
<field name="Slice Hashing Table Enable Mask" start="54" end="54" type="bool"/>
</instruction>
<instruction name="3DSTATE_AA_LINE_PARAMETERS" bias="2" length="3" engine="render">
src/intel/genxml/gen125.xml
+4 -1
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@@ -1296,7 +1296,10 @@
<field name="3D Scoreboard Hashing Mode" start="36" end="36" type="bool"/>
<field name="Subslice Hashing Table Enable" start="37" end="37" type="bool"/>
<field name="Slice Hashing Table Enable" start="38" end="38" type="bool"/>
<field name="Mask" start="48" end="63" type="mbo"/>
<field name="Cross Slice Hashing Mode Mask" start="48" end="49" type="uint"/>
<field name="3D Scoreboard Hashing Mode Mask" start="52" end="52" type="bool"/>
<field name="Subslice Hashing Table Enable Mask" start="53" end="53" type="bool"/>
<field name="Slice Hashing Table Enable Mask" start="54" end="54" type="bool"/>
</instruction>
<instruction name="3DSTATE_AA_LINE_PARAMETERS" bias="2" length="3" engine="render">
src/intel/vulkan/genX_state.c
+1
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@@ -147,6 +147,7 @@ genX(emit_slice_hashing_state)(struct anv_device *device,
anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {
p.SubsliceHashingTableEnable = true;
p.SubsliceHashingTableEnableMask = true;
}
#endif
}