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Author SHA1 Message Date
Paulo Zanoni
31f720fd6e anv/trtt: join L1 writes into a single MI_STORE_DATA_IMM when possible 
If the addresses are sequential, we can emit only a single
MI_STORE_DATA_IMM instruction. This is a very common case, it should
save us some space: 4 bytes per extra_write.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25512>
 2023-11-17 17:58:28 +00:00
Paulo Zanoni
ccb30ae0cd anv/sparse: fix limits.sparseAddressSpaceSize when using vm_bind 
When using vm_bind (not TR-TT), in practice sparse addresses will be
allocated from the high_heap, so narrow down the available
sparseAddressSpaceSize from the whole address space to the part we can
actually allocate things from.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25512>
 2023-11-17 17:58:28 +00:00
Paulo Zanoni
04bfe828db anv/sparse: allow sparse resouces to use TR-TT as its backend 
TR-TT is a hardware feature supported by both i915.ko and xe.ko, which
means we can now finally have Sparse Resources on i915.ko and we also
have 2 options for xe.ko (and whatever is the best should be the
default).

In this patch we use batch commands to write the page tables and
forever keep them in device memory. We maintain a mirror of both the
L3 and and L2 tables because that helps us never having to read the
tables that are in device memory.

We still have some things to improve, but with this commit, workloads
that didn't work at all due to the lack of sparse resources should
at least run.

This is still all disabled by default in i915.ko, you can turn it on
by exporting ANV_SPARSE=1 before launching the applications. For
xe.ko, switch the default with ANV_SPARSE_USE_TRTT=1.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25512>
 2023-11-17 17:58:28 +00:00
Rhys Perry
a279767424 ac/gpu_info: update conformant_trunc_coord comment 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25911>
 2023-11-17 15:15:28 +00:00
Rhys Perry
9e9eb87dd3 radv: enable radv_disable_trunc_coord for vkd3d-proton/DXVK 
This fixes diagonal SSAO artifacts in some games.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9253
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6395
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25911>
 2023-11-17 15:15:28 +00:00
Rhys Perry
4d2a3b9573 radv: add radv_disable_trunc_coord option 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25911>
 2023-11-17 15:15:27 +00:00
Eric Engestrom
1b18ca83fa amd/ci: avoid re-running all the test jobs when changing the expectations for only one of them 
Previously, any change to any job would trigger every job.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26127>
 2023-11-17 14:22:46 +00:00
Alyssa Rosenzweig
0f0f6c6227 nir/validate: Specialize if source validation 
Yet another bit of branchiness we should tame. 99% of the time, sources are not
for if's, so we shouldn't need to do the extra checking to handle that 1%.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
88d0fd03d6 nir/validate: Split out validate_sized_src 
We don't check the sizes for ALU srcs, which is the hot path here, so split out
that simplified version for ALU instructions to use, while deriving a sized
version for other kinds of instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
bfcc323954 nir/validate: Inline validate_ssa_src 
There's no more nir_register.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
bfdb2862d6 nir/validate: Drop stale todo 
We have dominance validation elsewhere in the file.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
9f341cefbb nir/validate: Don't check dimensions in validate_def 
Instead, check it at the call sites when actually required (basically just
intrinsics), reducing the branching required when not (ALU validation, the
hottest of hot paths for CI).

IMHO this is more obvious too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
d2b1e6bed0 nir/validate: Use unlikely for validate_assert 
No apparent performance difference, but documents the intention.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
e9d185dccf nir/validate: Don't validate out-of-bounds channels 
Nothing should ever be reading them, they logically do not exist. So there's no
point validating them, especially when the validation in question is so useless
(just checking the bit width, without any semantic awareness). Yet now that we
support vec16, this loop is quite hot even on scalar ISAs, and rather
pointlessly so. Just remove it and bring the ALU src validation complexity to
O(# of channels in source) instead of O(max # of channels in NIR).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
8d5a1e5a77 nir/validate: Don't spam nir_alu_instr_channels 
It doesn't inline and so is about 1% of M1 CTS time. Expand out the definition
and simplify the logic. Honestly, I think this is clearer too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
1786032029 nir/validate: Optimize ssa_srcs set 
Profiling showed that maintaining this ssa_srcs set consumes ~3% of CTS time
with a debugoptimized build. Unfortunately, we really do benefit from getting
this coverage in CI. So rather than remove the validation, let's optimize the
data structure used so we can keep the coverage at a fraction of the cost.

The expensive piece is the pointer set, which is backed by a relatively
expensive hash table. It would be much cheaper to use an invasive set instead,
with a single "present" bit. We don't want to bloat nir_src for this, however
there's an easy solution: use a tagged pointer to steal a bit in the nir_src for
the job. We untag everything at the end of validation (and this meta-invariant
is asserted with an auxiliary counter), so while we mutate the IR while
validating, the mutations do not escape nir_validate.

We tag the parent pointer and not the def pointer, because it is dramatically
less used and therefore has far fewer disrupted call sites.

The M1 job is improved from 3:03 to 2:55 of deqp-runner reported time, which is
excellent.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Alyssa Rosenzweig
6d73f62e42 nir: Simplify nir_alu_instr_channel_used definition 
Deduplicates the "get # of channels" logic which was the same between the
helpers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26084>
 2023-11-17 09:36:08 -04:00
Violet Purcell
667de678a0 gallium: Fix undefined symbols in version scripts 
Currently, multiple version scripts unconditionally use symbols from gallium
drivers that may not be enabled, which causes linking to fail with
--no-undefined-version (as is default in LLD 17), and can cause issues
with LTO. This commit adds logic to generate version scripts based on the
enabled gallium drivers, ensuring only defined symbols are used.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8003
Signed-off-by: Violet Purcell <vimproved@inventati.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25551>
 2023-11-17 12:35:24 +00:00
Lionel Landwerlin
c76cb19b01 anv/blorp: move helper function about BTI changes to blorp 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
 2023-11-17 10:17:51 +00:00
Lionel Landwerlin
1b6fe35ec8 anv: get rid of the duplicate pipeline fields in command buffer state 
This can be error prone if you forget to update one.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
 2023-11-17 10:17:51 +00:00
Lionel Landwerlin
ec3f8c0d42 intel/blorp: move Wa_18019816803 out of blorp code 
The driver already need to track this WA for blorp. We can completely
remove any blorp code dealing with this and instead have the flush
required by the workaround be combined with potential other flushes
the driver already has to insert before blorp operations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
 2023-11-17 10:17:51 +00:00
Lionel Landwerlin
6e85fa8a80 intel/decoder: handle 3DPRIMITIVE_EXTENDED in accumulated prints 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
 2023-11-17 10:17:51 +00:00
Lionel Landwerlin
9689607f10 anv: fix dirty state tracking for 3DSTATE_PUSH_CONSTANT_ALLOC 
ANV_CMD_DIRTY_PIPELINE also includes reprogramming of
3DSTATE_PUSH_CONSTANT_ALLOC_* instructions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
 2023-11-17 10:17:51 +00:00
Lionel Landwerlin
1257d08bcb anv: fix CC_VIEWPORT pointer dirty after blorp/simple-shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
 2023-11-17 10:17:51 +00:00
Lionel Landwerlin
e517b1e095 anv: fix missing naming for dirty bit 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
 2023-11-17 10:17:51 +00:00
Lionel Landwerlin
1a1747712c anv: fix source_hash propagation with libraries 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247>
 2023-11-17 10:17:51 +00:00
Daniel Schürmann
f2bb7b185d aco: delete instruction selection for boolean subgroup operations 
These are now lowered in NIR.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218>
 2023-11-17 09:45:40 +00:00
Daniel Schürmann
88afbbba11 nir: optimize open-coded quadVote* directly to new nir_quad intrinsics 
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218>
 2023-11-17 09:45:40 +00:00
Connor Abbott
0d186d356c amd: Enable boolean subgroup lowering 
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218>
 2023-11-17 09:45:40 +00:00
Connor Abbott
1dab2c5bd2 nir/subgroups: Add option to lower Boolean subgroup reductions 
This will be useful for AMD, and probably Intel as well.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218>
 2023-11-17 09:45:40 +00:00
Connor Abbott
387e698bde amd: Implement quad_vote intrinsics 
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218>
 2023-11-17 09:45:40 +00:00
Connor Abbott
1cfb0ae92c nir: Add quad vote intrinsics 
Both Intel and AMD have special hardware support for these.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218>
 2023-11-17 09:45:40 +00:00
Daniel Schürmann
27734c52eb nir/lower_subgroups: optimize reductions with cluster_size == 1 
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218>
 2023-11-17 09:45:40 +00:00
Boris Brezillon
9ac3117e3e panfrost: Emit image attribs for compute in panfrost_update_shader_state() 
This will make the job-frontend split easier, and it also makes sense
to update image attributes here for compute.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:11 +00:00
Boris Brezillon
3db963a135 panfrost: Emit attribs in panfrost_update_state_3d() on bifrost/midgard 
The dirty state tracking should allow us to conditionally re-emit the
vertex attribute and attribute buffer arrays if something relevant
changed.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
ac486a0115 panfrost: Kill unused panfrost_batch::polygon_list field 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
8ed471a339 panfrost: Flag the right shader when updating images 
Fixes: fab1fabb4f ("panfrost: Dirty track fragment images")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
1d4fa05b78 pan/decode: Fix the pan_unpack() call for JUMP instruction unpacking 
We are unpacking a CALL instead of JUMP instruction. It doesn't
make a difference because the instruction layout is the same,
but let's fix that for the sake of correctness.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
238f9a4498 pan/decode: Make CSF decoding more robust to NULL pointers 
Some staging registers might be NULL, either because some arguments are
optional, or because the command stream is malformed. In any case, being
robust to such situations it probably a good thing.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
7dd610f908 pan/decode: Print the resource table label 
Useful to quickly spot which stage of the pipeline is using a resource
table.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
408b3f3ced pan/genxml: Fix 'Shader Program' descriptor definition on v9 and v10 
Bit 8 in the descriptor is not encoding the primary/secondary shader
information. It's a per shader-type field.

For fragment shader descriptors, it describes what the coverage bitmask
contains for per-sample execution:
- DX-style: bits for all covered samples are set
- GL-style: only the bit for the sample the shader is executed on is set

For vertex shader, it encodes the warp limit we want to apply to the
shader execution.

Patch the existing code to match the new semantics.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
790d4422b2 pan/bo: Make sure we catch refcnt underflows 
Recently had to debug an unbalanced ref/unref situation in some
code I added, and having an assert(refcnt > 0) in
panfrost_bo_unreference() would have made this simpler, so let's
add one.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
46d2748a93 panfrost: Fix format_minimum_alignment() for v6- 
Alignment should be power of two, so I suspect we meant 64 not 63.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Boris Brezillon
6e166af59e pan/genxml: Fix "{Last,First} Heap Chunk" field position 
Those two fields were swapped.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26221>
 2023-11-17 09:29:10 +00:00
Samuel Pitoiset
c5e6edcddf radv: check earlier if a graphics pipeline can force VRS per vertex 
When a graphics pipeline already enables VRS, forcing VRS isn't
possible, check this earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26248>
 2023-11-17 08:39:48 +00:00
Samuel Pitoiset
61c3796a95 radv: remove redundant check when forcing VRS rates 
If force_vrs_per_vertex is TRUE, the primitive shading rate varying is
always written.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26248>
 2023-11-17 08:39:48 +00:00
Samuel Pitoiset
d679d12359 aco: remove useless nir_intrinsic_load_force_vrs_rates_amd 
It's lowered earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26248>
 2023-11-17 08:39:48 +00:00
Samuel Pitoiset
d01b7b0fd4 zink/ci: add a manual job on radv-navi31 
The run is sequential for now because otherwise a lot of AMDGPU errors
are reported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25459>
 2023-11-17 08:14:59 +00:00
Eric Engestrom
a5e20a5c31 ci_run_n_monitor: require user to add an explicit .* at the end if jobs like *-full are wanted 
Most of the time, these jobs are not wanted, so let's make this a full
match instead of prefix match so that users only get what they ask for.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26066>
 2023-11-17 08:12:31 +00:00
Eric Engestrom
ce7cda417f intel/dev: use libdrm.h wrapper to support builds without libdrm 
Fixes part of: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10159

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26236>
 2023-11-17 07:38:33 +00:00