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Author SHA1 Message Date
Yonggang Luo 035e55f5ac mapi: Now _glapi_get_dispatch_table_size always equal to sizeof(struct _glapi_table) / sizeof(void *) 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23822>
 2023-06-27 11:38:59 +00:00
Yonggang Luo e72a879de0 mapi: Fixes compile error with build option "-D shared-glapi=disabled" 
Fixes: 398a8d43dc ("mapi: Delete dynamic stub generation.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9245

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23822>
 2023-06-27 11:38:59 +00:00
Karmjit Mahil d53c751328 pvr: Change winsys flag defines to bitfields 
Makes it easier to see which flags are set while debugging, and
prevent errors where the `BITFIELD_BIT()` is missing or using the
wrong flag for something.

Some fields have also been renamed to better fit with the naming
scheme around the code base.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23765>
 2023-06-27 11:11:03 +00:00
Karmjit Mahil 4e6444af0b pvr: Fix missing BITFIELD_BIT for winsys frag job flag 
On submission SPMSCRATCHBUFFER was acting like GET_VIS_RESULT +
DEPTH_BUFFER_PRESENT. This was causing hardware resets on barrier
stores as the depth buffer isn't actually present so the
store would be carried out to a NULL address.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23765>
 2023-06-27 11:11:03 +00:00
Yonggang Luo 739ba18c79 util: include "util/compiler.h" instead of "pipe/p_compiler.h" 
And pipe/p_compiler.h are removed as it not used any more

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:30 +08:00
Yonggang Luo 0d82c0a026 util: Merge p_compiler.h into src/util/compiler.h 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:30 +08:00
Yonggang Luo b7b4e53404 treewide: style fixes after replace the usage of ubyte/ushort with uint8_t/uint16_t 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:30 +08:00
Yonggang Luo e53915828f treewide: Replace the usage of ubyte/ushort with uint8_t/uint16_t 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:29 +08:00
Yonggang Luo 05b840521a treewide: Replace the usage of TRUE/FALSE with true/false 
this is a separate patch as it's won't affect the code style

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:28 +08:00
Yonggang Luo 49e84fdad2 treewide: style fixes after replace usage of boolean to bool 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:28 +08:00
Yonggang Luo 7b45a0bd66 treewide: replace usage of boolean to bool 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:27 +08:00
Yonggang Luo b65e745168 llvmpipe: altivec.h inclusion in -std=c++98..11 causes bool to be redefined 
So we carefully include altivec.h in lp_setup_tri.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:27 +08:00
Yonggang Luo 07cb3c0e31 gallium/draw: Replace the usage of ushort to uint16_t in files that can not found by tools 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:26 +08:00
Yonggang Luo 542f00b5f1 hud: Use bool/true/false to replace boolean/TRUE/FALSE in hud/hud_context.c 
auto tools can not find and replace
```
#define HUD_DEFAULT_VISIBILITY TRUE
```
So did the of this line manually,

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
 2023-06-27 18:18:26 +08:00
Erik Faye-Lund e5aec68ce7 aux/indices: use stdint.h types 
These generated sources uses older, less portable types such as ubyte,
ushort and uint. But we have stdint.h everywhere now, so let's use those
types instead.

To stay consistent, let's talk about UINT8 etc instead of UBYTE for the
entirety of the u_indices infrastructure.

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23853>
 2023-06-27 09:46:33 +00:00
Christian Gmeiner 96c99bc2d9 etnaviv: linker: add fallback lookup to VARYING_SLOT_BFC[n] 
There are valid NIR shaders pairs where the vertex shader has
a VARYING_SLOT_BFC0 shader_out and the corresponding framgent
shader has a VARYING_SLOT_COL0 shader_in.
So at link time if there is no matching VARYING_SLOT_BFC[n],
we must map VARYING_SLOT_BFC0[n] to VARYING_SLOT_COL[n].

Example shader pair from 'spec@!opengl 2.0@vertex-program-two-side back':

shader: MESA_SHADER_VERTEX
source_sha1: {0xf916f77d, 0xffa6ab5e, 0x160976a7, 0xb59fe59c, 0x92e8f3f6}
name: GLSL3
internal: false
stage: 0
next_stage: 4
inputs_read: 0
outputs_written: 0,13
subgroup_size: 1
bit_sizes_float: 0x20
bit_sizes_int: 0x20
first_ubo_is_default_ubo: true
flrp_lowered: true
inputs: 1
outputs: 2
uniforms: 0
decl_var shader_in INTERP_MODE_NONE vec4 gl_Vertex (VERT_ATTRIB_POS.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_BackColor (VARYING_SLOT_BFC0.xyzw, 1, 0)
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = deref_var &gl_Vertex (shader_in vec4)
        vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0)
        vec4 32 ssa_2 = load_const (0x00000000, 0x00000000, 0x3f000000, 0x00000000) = (0.000000, 0.000000, 0.500000, 0.000000)
        vec1 32 ssa_5 = deref_var &gl_BackColor (shader_out vec4)
        vec4 32 ssa_11 = mov ssa_2
        vec4 32 ssa_13 = fsat ssa_11
        intrinsic store_deref (ssa_5, ssa_13) (wrmask=xyzw, access=0)
        vec1 32 ssa_7 = deref_var &gl_Position (shader_out vec4)
        vec4 32 ssa_12 = mov ssa_1
        intrinsic store_deref (ssa_7, ssa_12) (wrmask=xyzw, access=0)
        /* succs: block_1 */
        block block_1:
}

shader: MESA_SHADER_FRAGMENT
source_sha1: {0x5059da66, 0x00c609e5, 0x5329c39a, 0x13e2fc88, 0x8e68cb71}
name: GLSL3
internal: false
stage: 4
next_stage: 4
inputs_read: 1
outputs_written: 2
subgroup_size: 1
first_ubo_is_default_ubo: true
flrp_lowered: true
inputs: 1
outputs: 1
uniforms: 0
decl_var shader_in INTERP_MODE_NONE vec4 gl_Color (VARYING_SLOT_COL0.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0)
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = deref_var &gl_Color (shader_in vec4)
        vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0)
        vec1 32 ssa_2 = deref_var &gl_FragColor (shader_out vec4)
        intrinsic store_deref (ssa_2, ssa_1) (wrmask=xyzw, access=0)
        /* succs: block_1 */
        block block_1:
}

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23850>
 2023-06-27 09:26:40 +00:00
Christian Gmeiner f9e6069959 etnaviv: nir: call nir_remove_dead_variables(..) before linking setup 
There are cases where there is a chain to an unused nir variable that get removed
by nir_opt_dce. This breaks our current linker as the variable can still be accessed
via nir_foreach_shader_in_variable(..) macro.

So lets call nir_remove_dead_variables(..) just before we setup our linking.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23673>
 2023-06-27 09:10:17 +00:00
Christian Gmeiner 5f9ac20116 ir3/analyze_ubo_ranges: Move IR3_DBG_NOUBOOPT check 
There is no need to walk the hole nir shader if IR3_DBG_NOUBOOPT
is used.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23854>
 2023-06-27 08:19:10 +00:00
Iago Toral Quiroga 03ad1d5ab6 v3dv: don't use the TLB path if we might be copying partial tiles 
With TLB paths we are always storing full tiles, so we can't use it
if the regions we store are not a multiple of the tile size (or the
full image).

Unfortunately, at the point we call this we don't usually have the
tile size yet so for now we skip the path if we are not copying
full mip levels.

Fixes various CTS fails in:
dEQP-VK.ycbcr.copy.*.optimal*buffer_optimal*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23739>
 2023-06-27 09:04:20 +02:00
Iago Toral Quiroga cec030a233 v3dv: fix slice size for miplevels >= 2 
We want to store the slice size in pixels not the level size
after padding to a power of 2 we use miplevels >= 2.

Fixes: 1cb2d2a5ee ('v3dv: store slice dimensions in pixels')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23739>
 2023-06-27 09:04:20 +02:00
Konstantin Seurer 107d29765b docs: Update envvars used for tracing 
Updates the environment variables reference to document the new common
tracing infrastructure.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer b0beca8c7a vulkan/rmv,radv: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer e0641ed59f radv/rgp: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer 3e11640127 radv/rra: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer 291fa05545 vulkan/wsi/x11: Capture traces using a hotkey 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer 15d6618a12 radv: Add radv_trace_mode 
...and add the RADV specific trace modes to the VK instance.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer 70489edce4 vulkan: Common trace capturing infrastructure 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer 3b83a60c95 meson: Add a xcb-keysyms dependency 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer 7a7b1a4f71 radv: Call radv_pipeline_init_scratch per shader 
Compute pipelines only have one shader, which was not handled correctly
in the case of ray tracing pipelines. Adding radv_shader as an argument
allows us to handle the ray tracing prolog. The original loop is inlined
into its only user (radv_pipeline_graphics.c).

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23812>
 2023-06-27 06:04:18 +00:00
Sagar Ghuge 957d7644aa intel/ds: Track CCS cache flush bit 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 16:08:20 -07:00
Sagar Ghuge 5a272b5ed8 iris: implement recommended flush/wait of AUX-TT invalidation 
This patch implements the recommended flush/wait of AUX-TT invalidation
according to per command streamer (engine).

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 16:08:15 -07:00
Sagar Ghuge 6be75d8aa2 iris: Fix AUX-TT invalidation 
In order to make sure RCS engine is idle, we need to add
DC flush + CS stall + Render target Cache flush + Depth Cache
on Gfx 12 and additional CCS cache flush on Gfx12.5.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 15:57:39 -07:00
Sagar Ghuge 26a7e997fb iris: Add CCS cache flush bits 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 15:57:39 -07:00
Sagar Ghuge e88eac5b6c anv: implement recommended flush/wait of AUX-TT invalidation on compute 
This patch implements the recommended flush/wait of AUX-TT invalidation
for compute/render command streamer.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 15:57:39 -07:00
Sagar Ghuge 012ff791fb anv: Fix AUX-TT invalidation 
In order to make sure RCS engine is idle, we need to add
DC flush + CS stall + Render target Cache flush + Depth Cache
on Gfx 12 and additional CCS cache flush on Gfx12.5.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 15:57:39 -07:00
Sagar Ghuge 0b42a6c3b5 anv: Add CCS cache flush bits to anv_pipe_bits 
This will help us to flush the entries out of the CCS cache.

v2:
- Move enum value close to HW bits section (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 15:57:39 -07:00
Sagar Ghuge f592727130 intel/genxml: Add Compute/Blitter CCS aux invalidation register 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 15:57:39 -07:00
Sagar Ghuge 55d9959e67 intel/genxml: Add CCS cache flush field to PIPE_CONTROL 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
 2023-06-26 15:57:39 -07:00
Juan A. Suarez Romero 99502b42b4 vc4/v3d/ci: update expected results 
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23862>
 2023-06-26 18:44:16 +02:00
Vitaliy Triang3l Kuzmin f9e6d35f65 radv: Enable VK_EXT_fragment_shader_interlock 
ACO only currently - not available in LLVM.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 8a8f2edd50 zink/ci: Add broken fragment shader interlock test to RADV flakes 
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin ec0778f59e radv: Disable VRS forcing with Primitive Ordered Pixel Shading 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 787a553262 radv: Apply the POPS missed overlap hardware bug workaround 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 647952c8e3 ac/gpu_info: Check whether the device has the POPS missed overlap bug 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 3831860b20 radv: Handle Primitive Ordered Pixel Shading in DB_SHADER_CONTROL 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 37e325fe15 radv: Enable the null export workaround with POPS 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 7eabc5d6fc radv: Enable POPS collision wave ID shader argument 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 50e680d05a radv: Declare POPS collision wave ID shader argument 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 1812819e66 radv: Ensure 1x1 shading rate on GFX10.3 with interlock execution mode 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin 08c582ea69 radv: Detect the use of Primitive Ordered Pixel Shading 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00