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Author SHA1 Message Date
Faith Ekstrand
a2a0cef9f4 meson: Update our rust dependencies 
These are the package versions currently shipped by Fedora. This allows
using system packages by setting

    export MESON_PACKAGE_CACHE_DIR=/usr/share/cargo/registry/

Of course, other distros may place it somewhere else.

Ubuntu matches versions on syn and unicode-ident but is a tiny bit off
on quote and proc-macro2. However, given how far I was able to bump the
versions with only a tiny meson tweak to syn, I think it should work
with the Ubuntu versions as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26726>
 2023-12-18 18:33:53 +00:00
Michel Dänzer
f0594915e6 glx: Handle IGNORE_GLX_SWAP_METHOD_OML regardless of GLX_USE_APPLEGL 
Avoids tons of

 WARNING: unknown fbconfig attribute from server: tag 0x8060 value 0x8063

messages with LIBGL_DEBUG=verbose.

Fixes: e64ab3e4a9 ("glx: Delete support for GLX_OML_swap_method.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26685>
 2023-12-18 17:52:09 +00:00
Michel Dänzer
9548f969bd gallium/dri: Return __DRI_ATTRIB_SWAP_UNDEFINED for _SWAP_METHOD 
In contrast to __DRI_ATTRIB_SWAP_EXCHANGE, this is compatible with Mesa
< 23.3 on the client side.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10080
Fixes: e64ab3e4a9 ("glx: Delete support for GLX_OML_swap_method.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26685>
 2023-12-18 17:52:09 +00:00
Faith Ekstrand
290d958c63 nak/nir: Set nir_lower_io_lower_64bit_to_32 for varyings 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:29 +00:00
Faith Ekstrand
a9fb7b0280 nak: Implement b2f64 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:29 +00:00
Faith Ekstrand
26d649f120 nak: Fix nir_op_f2f64 
We were only allocating one register

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:29 +00:00
Faith Ekstrand
7ced1d3648 nak: Wire up 64-bit nir_op_fadd/ffma/fmul and comparisons 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
995eea8d04 nak: Split fmul/ffma handling from fmulz/ffmaz 
They're enough of a special case that things are going to get confusing
when we start adding bit sizes to fmul/ffma.  Let's make them a special
case so they can assert all their things.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
1236c5d4f1 nak: Add the rest of the double-precision ops 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
2f899f44eb nak: Rework encoding of ALU instructions on SM70+ 
The main change here is that we match on src2 first and then src1.  This
lets make some of the src2 code common because src2 never moves around
if it's a register.  This change also has another subtle effect: None
sources now work everywhere.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
c53f562d1a nak: OpDAdd doesn't have saturate 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
ada338bfcc nak/sm70: Allow src2 of 3src ops to be an immediate 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
8b2232906e nak: Pass SrcTypes around instead of RegFile in legalize 
We need to be able to tell the difference between `F64` and other GPR
source types.  In order for this to work, we also have to tighten up
some of the requirements round GPR and SSA sources.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
d24eb539c5 nak: Make OpAtom::cmpr a GPR source 
We set it to Zero for atomics other than CmpExch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
3b6e6e985e nak: Copy propagate and constant fold OpPrmt 
This comes up fairly frequently in int64 and fp64 use-cases.  In
particular, we see a lot of `prmt rZ 0x4444 rZ` which is just zero.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
9ad5b544d8 nak: Fix copy-prop for fp64 
For propagating OpDAdd, we need to check for negative zero because
negative zero is the no-op, not add with zero.  We were also propagating
the upper and lower halves of fp64 sources wrong.  While we're here, use
`let ... else` instead of an `if let` pattern a couple places.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Faith Ekstrand
d41b0a2bf5 nak: Move the copy detection part of opt_copy_prop to a helper 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
 2023-12-18 17:35:28 +00:00
Connor Abbott
0b2e48f432 freedreno/afuc: Fix gen autodetection for a7xx 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
 2023-12-18 17:01:35 +00:00
Connor Abbott
ae9604c29e freedreno/afuc: README updates for a7xx 
Mention the introduction of LPAC/BR/BV, and explain the shared control
reg space.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
 2023-12-18 17:01:35 +00:00
Connor Abbott
5ca347e727 freedreno: Update more control/pipe registers for a7xx 
Copy over control registers that are mostly the same from a6xx and add a
definition of the EVENT_CMD pipe register, which is updated for a7xx
events.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
 2023-12-18 17:01:35 +00:00
Connor Abbott
d01be55340 freedreno/afuc: Decode (sdsN) modifier 
This removes the last unknown flag from read/write instructions.

Because we now handle the write in CP_SET_DRAW_STATE more correctly when
emulating, we also have to update the control register definitions and
draw state emulation code to adjust.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
 2023-12-18 17:01:35 +00:00
Connor Abbott
55985b7301 freedreno/afuc: Add syntax for pre-increment addressing 
This is inspired by the ARM syntax.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
 2023-12-18 17:01:35 +00:00
Connor Abbott
579227e028 freedreno/afuc: Use SQE registers for call stack 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
 2023-12-18 17:01:35 +00:00
Connor Abbott
da3cf26564 freedreno/afuc: Add separate "SQE registers" 
It seems like starting with a6xx, the SQE has a special register space
for reading/writing the state of the processor itself, mainly used for
saving/restoring its state in preemption. Add support for disassembling
it, removing one of the unknown flags bits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
 2023-12-18 17:01:35 +00:00
Connor Abbott
7c919f0406 freedreno/afuc: Handle store instruction on a5xx 
Turns out a5xx already had store, although not load. It was using the
high bit of the unknown flags for this.

Note that a6xx does use the high bit, and we fall back to not decoding
it at all here before properly decoding it in the next commit. Splitting
up the commits seems worth this small breakage.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
 2023-12-18 17:01:35 +00:00
Dudemanguy
cef345129f vulkan/wsi/wayland: fix wl_event_queue memory leak 
When creating the swapchain, this queue is created, but it was never
freed in wsi_wl_swapchain_free along with the rest of the resources.

Signed-off-by: Dudemanguy <random342@airmail.cc>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26052>
 2023-12-18 16:28:53 +00:00
Jordan Justen
30faa7a483 anv, iris, intel/genxml: Update 3DSTATE_HS for xe2 
Update 3DSTATE_HS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
8ba9988858 anv, iris, intel/genxml: Update 3DSTATE_GS for xe2 
Update 3DSTATE_GS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
1bc7c966f4 intel/batch_decoder: Update 3DSTATE_PS decoding for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
a659b1f0c0 anv, blorp, iris, intel/genxml: Update 3DSTATE_PS_EXTRA for xe2 
Update 3DSTATE_PS_EXTRA programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
5548e6a478 anv, blorp, iris, intel/genxml: Update 3DSTATE_VS for xe2 
Update 3DSTATE_VS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
f170995e66 anv, blorp, iris: Update 3DSTATE_PS programming for xe2 
Rework:
 * Jordan: Move code into intel_update_ps_state()

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun
80d9294d2d intel/isl: update 3DSTATE_STENCIL_BUFFER (xe2) 
Update xml file and adjust driver code to compile.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun
2a49a598ce intel/genxml: update 3DSTATE_DEPTH_BUFFER instruction (xe2) 
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Jordan Justen
99eadc2ecb intel/genxml: Add UNIFIED_COMPRESSION_FORMAT enum for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun
2c41811808 intel/genxml: update 3DSTATE_WM_HZ_OP instruction (xe2) 
The depth clear value is provided from 3DSTATE_WM_HZ_OP now.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun
5d4a995294 intel/genxml: Remove 3DSTATE_CLEAR_PARAMS instruction (xe2) 
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Rohan Garg
9512f61cd8 iris,isl: Adjust driver for several commands of clear color (xe2) 
The xe2 xml will be updated in following commits. Commit message
has been updated by Jianxun.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Job Noorman
2d273c520c ir3: lower 64b registers before creating preamble 
ir3_nir_lower_preamble cannot handle 64b @load/store_preamble so we have
to make sure ir3_nir_opt_preamble will never produce them. Up to now,
nir_lower_locals_to_regs was run after preamble lowering so 64b locals
could still be around when lowering the preamble. This patch moves
running this pass, as well as ir3_nir_lower_64b_regs, to before the
preamble lowering.

Fixed Piglit tests:
- spec@arb_gpu_shader_fp64@execution@fs-indirect-temp-double-dst
- spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-frexp-dvec4-variable-index

This patch has no impact on shader-db.

Note: a few cleanup passes used to be run after nir_lower_locals_to_regs
(nir_opt_algebraic, nir_opt_constant_folding) and after
ir3_nir_lower_64b_regs (nir_lower_alu_to_scalar, nir_copy_prop). As far
as I can tell, these are not necessary anymore when running the register
lowering earlier so this patch removes them.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26737>
 2023-12-18 14:52:02 +00:00
Job Noorman
6cad2fc230 nir: add helper to create cursor after all @decl_regs 
@decl_reg intrinsics must be in the first block so it's convenient to be
able to create an insertion point after all @decl_regs when the first
block needs to be split.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26737>
 2023-12-18 14:52:02 +00:00
Tatsuyuki Ishi
533ec9843e radv: Precompute shader max_waves. 
Doing it at bind-time causes a 1.4% overhead (among all driver calls) in
Overwatch 2. !24502 mentions that it can be precomputed in case overhead
is a concern, so do it here.

max_waves is stored directly in the radv_shader struct, because
ac_shader_config conforms to LLVM ABI and we cannot add anything custom,
and radv_shader_info needs to be determined from NIR only.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26692>
 2023-12-18 14:31:25 +00:00
Tatsuyuki Ishi
1161f22c27 radv: Move up radv_get_max_waves, radv_get_max_scratch_waves. 
To avoid forward declaration.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26692>
 2023-12-18 14:31:25 +00:00
Tatsuyuki Ishi
e444908d65 radv: Simplify shader config assignment. 
We don't hash this struct so direct assignment here is OK.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26692>
 2023-12-18 14:31:24 +00:00
Samuel Pitoiset
4353b0ad72 radv: move emitting the fb mip tail workaround when rendering begins 
It doesn't have to be emitted in the draw path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26589>
 2023-12-18 13:06:29 +00:00
Samuel Pitoiset
7dd7e551b1 radv: stop checking FMASK for the fb mip tail workaround 
Vulkan doesn't allow mipmaps with MSAA images, so checking for FMASK
shouldn't have any effect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26589>
 2023-12-18 13:06:29 +00:00
Samuel Pitoiset
57efe44f43 radv: add missing HTILE support for fb mip tail workaround 
PAL also applies to depth/stencil images with HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26589>
 2023-12-18 13:06:29 +00:00
Tapani Pälli
82553774e2 iris: use intel_needs_workaround with 14015055625 
This was missing from the FS stage primitive-id check. Also add usage
of macro to avoid running any extra code on platforms where this WA
would not apply.

Fixes: 0f14724039 ("iris: Implement Wa_14015297576")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26709>
 2023-12-18 11:14:11 +00:00
Martin Roukala (né Peres)
240d11eb8d Revert "ci: disable the valve-kws farm until it can be rebooted" 
This reverts commit 299cd1af82 as I
managed to reboot it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26733>
 2023-12-18 07:53:42 +00:00
Dave Airlie
f76f4be301 intel/compiler: move gen5 final pass to actually be final pass 
This got broken by the register conversion, this pass needs to be
after all the others.

Fixes: ce75c3c3fe ("intel: Switch to intrinsic-based registers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26731>
 2023-12-18 07:24:37 +00:00
Martin Roukala (né Peres)
299cd1af82 ci: disable the valve-kws farm until it can be rebooted 
We are having some issues related to serial consoles and I can't seem
to connect to the VPN to reboot the gateway.

So let's disable the farm until I get to it.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26730>
 2023-12-18 08:27:54 +02:00