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freedreno/afuc: Handle store instruction on a5xx

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Turns out a5xx already had store, although not load. It was using the
high bit of the unknown flags for this.

Note that a6xx does use the high bit, and we fall back to not decoding
it at all here before properly decoding it in the next commit. Splitting
up the commits seems worth this small breakage.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
This commit is contained in:
Connor Abbott
2023-12-11 20:04:32 +01:00
committed by Marge Bot
parent cef345129f
commit 7c919f0406
2 changed files with 32 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
src/freedreno/afuc/afuc.xml
View File

@@ -603,7 +603,7 @@ SOFTWARE.
</bitset>
<bitset name="#control" extends="#instruction-rep">
<field name="FLAGS" low="12" high="15" type="hex"/>
<field name="FLAGS" low="12" high="14" type="hex"/>
<field name="OFFSET" low="21" high="25" type="#src"/>
<encode>
@@ -611,8 +611,7 @@ SOFTWARE.
</encode>
</bitset>
<bitset name="store" extends="#control">
<gen min="6"/>
<bitset name="#store" extends="#control">
<display>
{REP}store {SRC}, [{OFFSET} + 0x{IMMED}], 0x{FLAGS}
</display>
@@ -625,7 +624,6 @@ SOFTWARE.
<field name="IMMED" low="0" high="11" type="hex"/>
<field name="SRC" low="16" high="20" type="#src"/>
<pattern low="27" high="31">10100</pattern>
<encode>
<map name="SRC">src->src1</map>
@@ -633,7 +631,19 @@ SOFTWARE.
</encode>
</bitset>
<bitset name="cwrite" extends="#control">
<bitset name="store" extends="#store">
<gen max="5"/>
<pattern low="27" high="31">10101</pattern>
<pattern pos="15">0</pattern>
</bitset>
<bitset name="store" extends="#store">
<gen min="6"/>
<pattern pos="15">0</pattern>
<pattern low="27" high="31">10100</pattern>
</bitset>
<bitset name="#cwrite" extends="#control">
<doc>Write to a control register.</doc>
<display>
{REP}cwrite {SRC}, [{OFFSET} + {CONTROLREG}], 0x{FLAGS}
@@ -650,6 +660,16 @@ SOFTWARE.
</encode>
</bitset>
<bitset name="cwrite" extends="#cwrite">
<pattern pos="15">1</pattern>
<gen max="5"/>
</bitset>
<bitset name="cwrite" extends="#cwrite">
<pattern pos="15">0</pattern>
<gen min="6"/>
</bitset>
<bitset name="load" extends="#control">
<gen min="6"/>
<doc>
@@ -662,6 +682,7 @@ SOFTWARE.
</display>
<field name="IMMED" low="0" high="11" type="hex"/>
<pattern pos="15">0</pattern>
<field name="DST" low="16" high="20" type="#dst"/>
<pattern low="27" high="31">10110</pattern>
@@ -687,12 +708,14 @@ SOFTWARE.
<bitset name="cread" extends="#cread">
<gen max="5"/>
<pattern pos="15">1</pattern>
<pattern low="27" high="31">10110</pattern>
</bitset>
<!-- a6xx shuffled around the cread opcode -->
<bitset name="cread" extends="#cread">
<gen min="6"/>
<pattern pos="15">0</pattern>
<!-- a6xx shuffled around the cread opcode -->
<pattern low="27" high="31">10111</pattern>
</bitset>

3
src/freedreno/registers/adreno/adreno_control_regs.xml
View File

@@ -12,6 +12,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 name="REG_WRITE_ADDR" offset="0x010"/>
<reg32 name="REG_WRITE" offset="0x011"/>
<doc> Controls high 32 bits used by store afuc instruction </doc>
<reg32 name="STORE_HI" offset="0x038"/>
<reg64 name="IB1_BASE" offset="0x0b0"/>
<reg32 name="IB1_DWORDS" offset="0x0b2"/>
<reg64 name="IB2_BASE" offset="0x0b4"/>