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radv: move emitting the fb mip tail workaround when rendering begins

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It doesn't have to be emitted in the draw path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26589>
This commit is contained in:
Samuel Pitoiset
2023-12-14 16:15:09 +01:00
committed by Marge Bot
parent 7dd7e551b1
commit 4353b0ad72
1 changed files with 2 additions and 8 deletions
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10
src/amd/vulkan/radv_cmd_buffer.c
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@@ -7450,7 +7450,6 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
* has been recorded without a framebuffer, otherwise
* fast color/depth clears can't work.
*/
radv_emit_fb_mip_change_flush(primary);
radv_emit_framebuffer_state(primary);
}
@@ -7801,6 +7800,8 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
S_028208_BR_X(render->area.offset.x + render->area.extent.width) |
S_028208_BR_Y(render->area.offset.y + render->area.extent.height));
radv_emit_fb_mip_change_flush(cmd_buffer);
if (!(pRenderingInfo->flags & VK_RENDERING_RESUMING_BIT))
radv_cmd_buffer_clear_rendering(cmd_buffer, pRenderingInfo);
}
@@ -9015,10 +9016,6 @@ radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info
cmd_buffer->state.last_index_type = -1;
}
/* Need to apply this workaround early as it can set flush flags. */
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
radv_emit_fb_mip_change_flush(cmd_buffer);
/* Use optimal packet order based on whether we need to sync the
* pipeline.
*/
@@ -9097,9 +9094,6 @@ radv_before_taskmesh_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_
ASSERTED const unsigned ace_cdw_max =
!ace_cs ? 0 : radeon_check_space(cmd_buffer->device->ws, ace_cs, 4096 + 128 * (drawCount - 1));
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
radv_emit_fb_mip_change_flush(cmd_buffer);
radv_emit_all_graphics_states(cmd_buffer, info);
si_emit_cache_flush(cmd_buffer);