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Author SHA1 Message Date
Marek Olšák
98b7c4ea09 st/mesa: optimize uploading zero-stride vertex attribs 
Instead of memcpy into a temporary array and then upload from that,
upload into a buffer directly.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19783>
 2022-12-09 03:18:53 +00:00
Marek Olšák
a18b9d071d st/mesa: remove alignment code from st_setup_current 
I was the one who added this code and it doesn't seem useful.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19783>
 2022-12-09 03:18:53 +00:00
David Heidelberg
1d5962b0e6 ci: fix missing line after adding austraincoder's farm killswitch 
Accidentally dropped.

Fixes: ff928d9567 ("ci: Allow disabling the whole of austriancoder's farm")

Reported-by: Ana Guerrero Lopez <anagl@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Ana Guerrero Lopez <anagl@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20236>
 2022-12-09 02:48:25 +00:00
Jordan Justen
0d9be82fe6 intel/genxml: Add genX_rt_pack.h 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20225>
 2022-12-09 01:43:39 +00:00
Lionel Landwerlin
b4b4294a78 intel/fs: add a saturation propagation test 
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20206>
 2022-12-09 00:39:05 +00:00
Oleksii Bozhenko
d5d8bb1dbb brw: fix saturate propagation region overlap range 
Fixes: 947c828d5c
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7691

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Oleksii Bozhenko <oleksii.bozhenko@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20206>
 2022-12-09 00:39:05 +00:00
Tapani Pälli
bc4b7de0d0 intel/fs: implement Wa_14017989577 
The first instruction of any kernel should have non-zero emask. This
restriction needs to be obeyed to avoid GPU hangs.

Patch adds a function to insert dummy mov as first instruction
to make sure this requirement is fulfilled.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20194>
 2022-12-08 23:58:32 +00:00
Chia-I Wu
5ba35fd6cc freedreno: fix compute shared_size underflow 
It caused ~5% of perf regression for some gfxbench benchmarks.

Fixes: b8d10d9e87 ("gallium: split up req_local_mem")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20219>
 2022-12-08 22:33:56 +00:00
Ruijing Dong
a7b3a279fb radeonsi/vcn: av1 film_grain output fix 
use film grain surface as the output instead of target,
which should be kept for DPB process.

fixed: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6903

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
 2022-12-08 21:59:24 +00:00
Ruijing Dong
af695149e9 frontends/va: pass in film_grain_target as new output 
In av1 film grain case, to use the film_grain_target
as the output, instead of target buffer, which is kept
as the input for DPB processing in film_grain output
scenario.

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
 2022-12-08 21:59:24 +00:00
Ruijing Dong
7e91f94864 frontneds/va: use current_display_picture from VA for film grain 
use the interface defined in vaapi for av1 film grain's output
https://github.com/intel/libva/blob/master/va/va_dec_av1.h#L296-L304

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Mark Thompson <sw@jkqxz.net>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
 2022-12-08 21:59:24 +00:00
Ruijing Dong
7f71f732ea frontends/omx: initialize film_grain_target 
set film_grain_target to NULL, and not using it
in omx path.

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
 2022-12-08 21:59:24 +00:00
Ruijing Dong
b70953f5ba gallium: add film_grain_target into av1 dec desc 
In vaapi, film_grain output will need to direct into
other output surface instead of the current render_target.

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
 2022-12-08 21:59:24 +00:00
Max Lee
2db09f5b22 drm-shim: add __readlink_chk as readlink with overflow check 
As per Linux Standard Base Core Specification 4.0, __readlink_chk
display value of a symbolic link, with buffer overflow checking.

if size > buflen, abort() is called.

Signed-off-by: Max Lee <endlesspring@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19045>
 2022-12-08 21:05:15 +00:00
Matt Coster
3068f046bc pvr: Check depth/stencil attachment is tile-aligned 
The hardware requires depth/stencil attachments to be size-aligned to
the zls tile size (as defined by rogue_get_zls_tile_size_xy()).

In practice however, this is a tiny edge case. The restriction only
applies during some operations, and any attachment larger than the tile
size will be twiddled and over-allocated into alignment beforehand.

This commit also adds the mentioned rogue_get_zls_tile_size_xy()
function. These values differ from the regular tile_size_{x,y} feature
values in some cases. Instead of including them as features as well, we
compute them directly.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20160>
 2022-12-08 14:53:13 +00:00
Matt Coster
2112a7d9ed pvr: Account for other depth formats in pvr_frag_state_stream_init() 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20160>
 2022-12-08 14:53:13 +00:00
Matt Coster
6404eee627 pvr: Add stencil support in render job setup 
The implementation here assumes separate depth and stencil attachments
are not possible, as they are in Vulkan without VK_KHR_dynamic_rendering
and before core 1.3.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20160>
 2022-12-08 14:53:13 +00:00
Christian Gmeiner
ff928d9567 ci: Allow disabling the whole of austriancoder's farm 
Add a global-level variable that allows disabling all jobs that would
have gone to my lab, to be used in case of outages.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18997>
 2022-12-08 14:09:39 +00:00
Samuel Pitoiset
011a0b97b2 radv,aco: move radv_ps_epilog_key to the graphics pipeline key 
To avoid redundant structs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20199>
 2022-12-08 13:28:00 +00:00
Samuel Pitoiset
67c9497435 radv: fix PS epilogs with RADV_PERFTEST=pswave32 
This option is rarely or even never used but it was broken. While we
are at it, remove radv_ps_epilog_key::wave32 because the wave size
can only be changed globally for PS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20199>
 2022-12-08 13:28:00 +00:00
Samuel Pitoiset
b7f49de625 radv,aco: use 8-bit for color_is_int{8,10} everywhere 
Do not need 32-bits because there is only up to 8 MRTs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20199>
 2022-12-08 13:28:00 +00:00
Samuel Pitoiset
9079bd821c radv,aco: rename color output related fields for consistency 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20199>
 2022-12-08 13:28:00 +00:00
Matt Coster
724e662948 pvr: Extract common code from pvr_CmdDispatch{,Indirect} 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20159>
 2022-12-08 13:10:35 +00:00
Matt Coster
46213744c7 pvr: Track max_shared_regs for compute jobs 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20159>
 2022-12-08 13:10:35 +00:00
Matt Coster
293230faf1 pvr: Refactor pvr_compute_pipeline and pvr_compute_pipeline_shader 
This brings the two structs more into line with their graphics
counterparts, and removes the extra member access previously required
to access almost all members of pvr_compute_pipeline.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20159>
 2022-12-08 13:10:35 +00:00
Tatsuyuki Ishi
327c906424 aco: Migrate RA to use std::optional 
The use of std::optional simplifies expressions and would be useful for some
upcoming RA tweaks.

C++17 has been available since the merge of rusticl and should be safe to use as
far as packaging is concerned.

A few style choices are:
- Testing for emptiness uses implicit bool conversion.
- Constructing an empty value uses {}.
- Constructing a filled value uses the implicit conversion constructor.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20125>
 2022-12-08 12:08:01 +00:00
Martin Roukala (né Peres)
a3249415e2 ci/valve-infra: use a new version of the mesa trigger 
This new version of the container will re-try up to 3 times to download
the job bucket, rather than failing directly. If the issue persists,
the job will still succeed, but not all artifacts will be present...

Fixes: #7809
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20203>
 2022-12-08 12:27:01 +02:00
Kenneth Graunke
bafbe7c23a intel/compiler: Set NoMask on cr0 access for float controls mode 
This is trying to clear a bit in the control register.  However, it's
executing with whatever channel mask happens to be active.  Typically
this is the one at the start of the program, so at least some channels
will be active.  Typically the first channel will be active due to
packed dispatch, but that's not always guaranteed.  Without NoMask,
the float controls writes may randomly not happen.

Recent GPUs also seem to have a hang issue when the first instruction in
the shader doesn't have any active channels.  Having an instruction with
NoMask at the start of the program works around the issue.  See HSD bug
14017989577.  In our case, the float controls preamble was breaking that
restriction every time, causing us to run into this problem frequently.

Thanks to Tapani Pälli for finding this hang issue, and Francisco
Jerez and Lionel Landwerlin for helping pinpoint this issue during
review of a workaround patch in !20194.

Fixes GPU hangs in Elder Scrolls Online, Witcher 3, and likely more.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7639
Fixes: 9da56ffc52 ("i965/fs: add emit_shader_float_controls_execution_mode() and aux functions")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20214>
 2022-12-08 09:54:09 +00:00
Gert Wollny
b6616b036f virgl: lower FMA and MULADD 
On the host we emit this as separate ops anyway, so avoid
wired optimizations in the guest that might introduce
difficult to optimize dependencies.

v2: update trace expectations - some minor accuracy changes
    are to be expected when fma is handled differently

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20182>
 2022-12-08 08:40:53 +00:00
Timothy Arceri
8d10a6835f glsl: dont create temps for builtin function inputs 
It's not valid to be copying input variables to temps when
inlining atomic memory, interpolateAt functions, etc. We got away
with this previously because tree grafting would clean up the
mess but we shouldn't depend on an optimisation to clean up
invalid IR. Also I hope to remove tree grafting in a follow up
merge request.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19890>
 2022-12-08 05:22:27 +00:00
Timothy Arceri
7b9ec592aa glsl: use ir_rvalue_visitor for function inlining 
This allows us to drop some duplicate code that is already in the
ir_rvalue_visitor. It also allows us to better replace rvalues
and handle swizzle in the following patch without having to add
even more duplicate code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19890>
 2022-12-08 05:22:27 +00:00
Yiwei Zhang
34b28cfb7d venus: scrub ignored fields for descriptor writes for push descriptor 
Fixes: 933ca11f1a ("venus: implement vkCmdPushDescriptorSetWithTemplateKHR")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20191>
 2022-12-08 01:56:35 +00:00
Iván Briano
e1ab7629f8 vulkan: VkPolygonMode has a bit more than two values 
Fixes: 9d0ed9cbcc ("vulkan: Add more dynamic rasterizer state")

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20212>
 2022-12-08 00:40:11 +00:00
Väinö Mäkelä
4035853523 hasvk: Report correct multisampling limits on gfx7 
Some limits reported by hasvk were too high, which caused CTS tests to
fail.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19393>
 2022-12-08 00:16:44 +00:00
Bas Nieuwenhuizen
513442dc32 aco: Add s_delay_alu support for GFX11+ 
Roughly copied from LLVM. This facilitates better ALU usage by
switching between waves when there is an ALU stall, which isn't
automatic anymore on GFX11.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19743>
 2022-12-07 22:05:25 +00:00
Bas Nieuwenhuizen
cd3bf56ace aco: Add helper to get cycle info for an instruction. 
For use in s_delay_alu tracking

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19743>
 2022-12-07 22:05:25 +00:00
Bas Nieuwenhuizen
352e492c7b aco: Add isTrans helper. 
For the s_delay_alu tracking.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19743>
 2022-12-07 22:05:25 +00:00
Samuel Pitoiset
bdb7fd69d6 radv: mark extendedDynamicState3SampleLocationsEnable as not required by Zink 
Only dynamic blend equation support is still required.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19924>
 2022-12-07 16:43:17 +01:00
Samuel Pitoiset
06a65be3d4 radv: advertise extendedDynamicState3LineRasterizationMode 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19924>
 2022-12-07 16:43:15 +01:00
Samuel Pitoiset
1009276312 radv: add support for dynamic line rasterization mode 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19924>
 2022-12-07 16:43:13 +01:00
Samuel Pitoiset
f992e663c7 radv: advertise extendedDynamicState3RasterizationSamples 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19924>
 2022-12-07 16:43:11 +01:00
Samuel Pitoiset
a2fe4e9b04 radv: add support for dynamic rasterization samples 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19924>
 2022-12-07 16:43:09 +01:00
Samuel Pitoiset
c88d4037aa radv: store the number of color/ds samples to the rendering state 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19924>
 2022-12-07 16:43:07 +01:00
Mihai Preda
613e9b8e7a nir: fix digit order in print_bitset() 
Also fix the leading curly for the new function definitions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19570>
 2022-12-07 12:59:33 +00:00
Mihai Preda
0320dbaff5 nir: print shader_info bools with the value 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19570>
 2022-12-07 12:59:33 +00:00
Mihai Preda
da2d36a9d5 nir: print shader_info inputs/outputs as bit ranges 
e.g.
inputs_read: 15-17
outputs_written: 0,32

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19570>
 2022-12-07 12:59:33 +00:00
Mihai Preda
89eca6a2fa radeonsi: add AMD_DEBUG=elements for printing vertex elements 
in si_create_vertex_elements()

This information is useful in debugging shader inputs/outputs

Sample output:
AMD_DEBUG=elements ./bin/arb_vertex_attrib_64bit-overlapping-locations shader -auto
elements[0]: offset  0, buffer_index 0, dual_slot 0, format  16, divisor 0
elements[1]: offset 16, buffer_index 0, dual_slot 0, format  16, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 104, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 105, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 106, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format  16, divisor 0
elements[1]: offset 16, buffer_index 0, dual_slot 0, format  16, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 104, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 105, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 106, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[1]: offset 16, buffer_index 0, dual_slot 1, format 107, divisor 0
elements[2]: offset 32, buffer_index 0, dual_slot 1, format 105, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[1]: offset 40, buffer_index 0, dual_slot 1, format 107, divisor 0
elements[2]: offset 56, buffer_index 0, dual_slot 1, format 105, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[1]: offset 64, buffer_index 0, dual_slot 1, format 107, divisor 0
elements[2]: offset 80, buffer_index 0, dual_slot 1, format 105, divisor 0

PIGLIT: {"result": "pass" }
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19570>
 2022-12-07 12:59:33 +00:00
Mihai Preda
6dd170e5a4 util: minor refactor _mesa_sha1_print() 
should not change the output; avoids an additional printf()
for the separator.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19570>
 2022-12-07 12:59:33 +00:00
Mihai Preda
e9f3f80b1d nir: print_shader_info(): brief output 
Make the shader_info printing less verbose by skipping the fields that
are likely not used (being zero).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19570>
 2022-12-07 12:59:33 +00:00
Mihai Preda
814ba7d13d nir: print_shader_info: print stage-specific shader info 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19570>
 2022-12-07 12:59:33 +00:00