radeonsi: add AMD_DEBUG=elements for printing vertex elements

in si_create_vertex_elements()

This information is useful in debugging shader inputs/outputs

Sample output:
AMD_DEBUG=elements ./bin/arb_vertex_attrib_64bit-overlapping-locations shader -auto
elements[0]: offset  0, buffer_index 0, dual_slot 0, format  16, divisor 0
elements[1]: offset 16, buffer_index 0, dual_slot 0, format  16, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 104, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 105, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 106, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format  16, divisor 0
elements[1]: offset 16, buffer_index 0, dual_slot 0, format  16, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 104, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 105, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 106, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[1]: offset 16, buffer_index 0, dual_slot 1, format 107, divisor 0
elements[2]: offset 32, buffer_index 0, dual_slot 1, format 105, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[1]: offset 40, buffer_index 0, dual_slot 1, format 107, divisor 0
elements[2]: offset 56, buffer_index 0, dual_slot 1, format 105, divisor 0
elements[0]: offset  0, buffer_index 0, dual_slot 0, format 107, divisor 0
elements[1]: offset 64, buffer_index 0, dual_slot 1, format 107, divisor 0
elements[2]: offset 80, buffer_index 0, dual_slot 1, format 105, divisor 0

PIGLIT: {"result": "pass" }
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19570>

src/gallium/drivers/radeonsi/si_pipe.c

@@ -81,6 +81,7 @@ static const struct debug_named_value radeonsi_debug_options[] = {
    {"vm", DBG(VM), "Print virtual addresses when creating resources"},
    {"cache_stats", DBG(CACHE_STATS), "Print shader cache statistics."},
    {"ib", DBG(IB), "Print command buffers."},
+   {"elements", DBG(VERTEX_ELEMENTS), "Print vertex elements."},
 
    /* Driver options: */
    {"nowc", DBG(NO_WC), "Disable GTT write combining"},

src/gallium/drivers/radeonsi/si_pipe.h

@@ -225,6 +225,7 @@ enum
    DBG_VM,
    DBG_CACHE_STATS,
    DBG_IB,
+   DBG_VERTEX_ELEMENTS,
 
    /* Driver options: */
    DBG_NO_WC,

src/gallium/drivers/radeonsi/si_state.c

@@ -4871,6 +4871,15 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count,
                                        const struct pipe_vertex_element *elements)
 {
    struct si_screen *sscreen = (struct si_screen *)ctx->screen;
+
+   if (sscreen->debug_flags & DBG(VERTEX_ELEMENTS)) {
+      for (int i = 0; i < count; ++i) {
+         const struct pipe_vertex_element *e = elements + i;
+         fprintf(stderr, "elements[%d]: offset %2d, buffer_index %d, dual_slot %d, format %3d, divisor %u\n",
+                i, e->src_offset, e->vertex_buffer_index, e->dual_slot, e->src_format, e->instance_divisor);
+      }
+   }
+
    struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
    struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
    STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);