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161702 Commits

Author SHA1 Message Date
Faith Ekstrand
965bbe5286 intel/fs: Rework the overlapping mov/vec case 
Now that we're using load/store_reg intrinsics, the previous checks for
registers aren't what we want.  Instead, we need to be looking for a mov
or vec where both the destination and a source are load/store_reg with
matching decl_reg.

Fixes: b8209d69ff ("intel/fs: Add support for new-style registers")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24310>
 2023-07-25 16:25:11 +00:00
Faith Ekstrand
45ee952efb intel/fs: Use write masks from store_reg intrinsics 
Fixes: b8209d69ff ("intel/fs: Add support for new-style registers")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24310>
 2023-07-25 16:25:10 +00:00
Faith Ekstrand
d89ca14e71 broadcom/compiler: Convert to new-style NIR registers 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Faith Ekstrand
355afc92d1 nir/schedule: Support load/store_reg 
These are tracked the same way as register reads and writes, allowing
them to be re-arranged as long as they respect dependencies within the
same reg.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Faith Ekstrand
6908814d46 vc4: Convert to new-style NIR registers 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Iago Toral Quiroga
dff85b6163 nir/trivialize: Move decl_reg to the start of the block 
This makes it so we never find a reg_decl in between a reg_store and the def
for its value, which helps avid inserting copy movs.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Alyssa Rosenzweig
0655bada4b nir/trivialize: Handle more RaW hazards 
Consider the snippet of NIR:

   div 32    %447 = @load_reg (%442) (base=0, legacy_fabs=0, legacy_fneg=0)
   div 32    %463 = @load_reg (%442) (base=0, legacy_fabs=0, legacy_fneg=0)
   con 32    %409 = iadd %17 (0x3), %447
                    @store_output (%182 (0x601), %463) (base=0, wrmask=x, component=0, src_type=invalid...
                    @store_reg (%409, %442) (base=0, wrmask=x, legacy_fsat=0)

The load_reg's are trivial, so the %442 read will get folded into store_output.
But under the old definition, the store_reg is also trivial so it gets folded
into the iadd... causing a read-after-write hazard and invalid code generation.

The fix is to amend our definition of store_reg triviality to account for loads
getting folded in. It's not good enough that there's no intervening load_reg,
there can also be no intervening source that gets chased to a load_reg. Handle
that case as well.

Identified in dEQP-VK.geometry.input.basic_primitive.triangles_adjacency on
V3DV.

Fixes: d313eba94e ("nir: Add pass for trivializing register access")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reported-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Faith Ekstrand
f8b69abbd4 nir/trivialize: Trivialize cross-block loads 
In order for a register load to be trivial, it cannot be used in any
block other than the one in which it is loaded.  We're not currently
explicitly doing anything to ensure this invariant holds.  It may be
that it holds regardless but I couldn't find any documented reason why
it should so let's explicitly handle that case.  Worst case, the newly
added code does nothing.

Fixes: d313eba94e ("nir: Add pass for trivializing register access")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Faith Ekstrand
f1f05cc7cf nir/trivialize: Maintain divergence information 
Because this pass is intended to be run after out-of-SSA and directly
before injesting the NIR into the back-end, it may come after divergence
analysis and needs to preserve the divergence information. Fortunately,
since all we ever do is insert nir_op_mov, this is easy.

Fixes: d313eba94e ("nir: Add pass for trivializing register access")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Faith Ekstrand
4fd257d20f nir: Properly handle divergence for load_reg 
This commit makes three changes:

 1. Default all newly created registers divergent because this is the
    safer default.

 2. Make divergence analysis do something sane with register divergence.
    It's not perfect because divergence analysis isn't able to prove
    registers divergent based on stores but at least if someone uses
    registers a bit they'll end up with safe defaults.  This matches
    what they'd get with nir_ssa_def_init().

 3. Make the load_reg() helper automatically propagate divergence from
    the register.  Because the defaults for both nir_ssa_def_init() and
    nir_decl_reg() are to mark everything divergent, this only means
    that nir_load_reg() of a uniform reg is now uniform.

Putting all these together, nir_from_ssa should now be producing
load_reg intrinsics with the proper uniform information.

Fixes: 7229bffcb1 ("nir: Add intrinsics for register access")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Alyssa Rosenzweig
91c3ee2412 pan/bi: Remove leftover include 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24153>
 2023-07-25 15:36:52 +00:00
Marcin Ślusarz
4f1125e4ae intel/compiler/test: fix crashes when TEST_DEBUG is set 
Dumping instructions requires that ISA info is not empty.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24274>
 2023-07-25 15:13:29 +00:00
Yonggang Luo
23a2b83639 lavapipe: fixes indent of function lvp_inline_uniforms 
The indent fixes are in separate patch is for easier to review

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:07 +00:00
Yonggang Luo
b4ed366d6b lavapipe: Convert to use nir_foreach_function_impl 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:07 +00:00
Yonggang Luo
d557169e81 zink: Convert to use nir_foreach_function_impl when possible 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:07 +00:00
Yonggang Luo
c7672f4fa5 freedreno: Switch to use nir_foreach_function_impl in tu_shader.cc 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:07 +00:00
Yonggang Luo
d45f846946 lima: Convert to use nir_foreach_function_impl when possible 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:06 +00:00
Antonio Gomes
29f4e7b215 rusticl/core: Make convert_spirv_to_nir output pair (KernelInfo, NirShader) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes
2448bdc81b rusticl/core: Delete KernelDevState and KernelDevStateInner 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes
58979e9247 rusticl/program: New helper functions to NirKernelBuild 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes
323dcbb4b5 rusticl: Move NirKernelBuild to ProgramDevBuild 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes
7ec9b9cd07 rusticl/compiler: Remove unnecessary functions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes
218dce5e38 rusticl: Move Cso to Program 
Commit got huge, but couldn't figure out a better way to split without
breaking stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes
11729e8311 rusticl/compiler: Add NirPrintfInfo 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes
e3169f624d rusticl/kernel: Add CsoWrapper 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes
07c8bce24d rusticl/kernel: Removing unnecessary clone in kernel launch 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
David Heidelberg
f49bfb1108 ci/freedreno: add a530 flake vs-lessthanequal-uvec4-uvec4 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24314>
 2023-07-25 09:26:12 +00:00
Illia Polishchuk
c1a02c0138 state_tracker: fix dereference before null check 
Coverity error
CID 1528178 (#1 of 1): Dereference before null check (REVERSE_INULL)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Polishchuk
34e47b40e6 glx: fix dead code when gc var cannot be null due to earlier check 
CID 1528170 (#1 of 1): Logically dead code (DEADCODE)
At condition gc, the value of gc cannot be NULL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Polishchuk
c2724b4d37 s/Intel: fix/anv: fix: potentially overflowing expression in genX 
CID 1528164 (#1 of 1): Unintentional integer overflow (OVERFLOW_BEFORE_WIDEN)
overflow_before_widen: Potentially overflowing expression
pool->n_passes * pool->khr_perf_preamble_stride with type
unsigned int (32 bits, unsigned) is evaluated using 32-bit arithmetic,
and then used in a context that expects an expression of type uint64_t (64 bits, unsigned).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Polishchuk
1cbf10ca88 iris: remove NULL check for already dereferenced pointer earlier 
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>

Found by Coverity.

CID: 1528158
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Abernikhin
33546705b5 i915: change format in dbg string 
Actually, uintptr_t is of type unsigned long, but the
debug line uses the %d format specifier, which expects an int.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Abernikhin <illia.abernikhin@globallogic.com>

Found by Coverity.

CID: 1515961
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Abernikhin
c22961571a state_tracker: moving initialisation of whandle out from if statement 
whandle initialization inside if statement but used also outside

Signed-off-by: Illia Abernikhin <illia.abernikhin@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Found by Coverity.

CID: 1516746
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Konstantin Seurer
ae18247e88 lavapipe: Advertise samplerYcbcrConversion 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer
32403c696b lavapipe: Implement samplerYcbcrConversion 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer
2667da5174 lavapipe: Fix binding immutable samplers with desc buffers 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer
da95f64a6f lavapipe: Store immutable_samplers as lvp_sampler array 
We will need this to access the ycbcr conversion.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer
7dc6c4b581 lavapipe: Remove dummy sampler ycbcr conversion 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer
dbbd84ce8b gallivm: Ignore nir_tex_src_plane 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer
c7914a84e9 gallivm: Fix subsampled format sampling under Vulkan 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer
1280cf5b2a draw: Do not restart the primitive_id at 0 
Otherwise the primitive_id will wrap around to 0 if more than 4096
patches are drawn.

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Samuel Pitoiset
df98dca7ad radv: pass submit info to radv_check_gpu_hangs() 
This will allow to dump preambles/postambles CS and eventually even
more CS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24191>
 2023-07-25 06:50:33 +00:00
Samuel Pitoiset
9c95a74e5e radv/amdgpu: rename old_ib to ib in radv_amdgpu_winsys_cs_dump() 
Forgot this variable when I renamed the ib_buffers array.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24191>
 2023-07-25 06:50:33 +00:00
Samuel Pitoiset
7eb1105829 radv/amdgpu: fix dumping CS with the chained IBs path 
ib_buffer is now NULL in both paths, and the first IB is the beginning
of the chain.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24191>
 2023-07-25 06:50:33 +00:00
Samuel Pitoiset
7f173d1ff3 radv: use next_stage for determining the stage to lower NGG 
If the next stage is FS, it's also the last VGT API stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset
340f74e468 radv: simplify getting next VS stage for VS prologs 
It's the VS shader info stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset
ca520c49f5 radv: determine as_ls earlier by using the next stage 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset
f68316d78b radv: determine ES info for VS/TES with GS earlier 
By using the next stage, it's possible to compute these information
earlier without having to link shaders info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset
4098e47ab6 radv: use the number of GS linked inputs to compute the ESGS itemsize 
It's similar.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset
7c2d38f4d1 radv: add a helper to compute the ESGS itemsize 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00