AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: simplify getting next VS stage for VS prologs

Browse Source 
It's the VS shader info stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
This commit is contained in:
Samuel Pitoiset
2023-07-20 17:11:50 +02:00
committed by Marge Bot
parent ca520c49f5
commit 340f74e468
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_cmd_buffer.c
+1 -1
View File
@@ -3768,7 +3768,7 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
key.as_ls = vs_shader->info.vs.as_ls && instance_rate_inputs;
key.is_ngg = vs_shader->info.is_ngg;
key.wave32 = vs_shader->info.wave_size == 32;
key.next_stage = ffs(cmd_buffer->state.active_stages) - 1;
key.next_stage = vs_shader->info.stage;
union vs_prolog_key_header header;
header.v = 0;