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radv: determine as_ls earlier by using the next stage

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
This commit is contained in:
Samuel Pitoiset
2023-07-21 11:10:37 +02:00
committed by Marge Bot
parent f68316d78b
commit ca520c49f5
1 changed files with 3 additions and 3 deletions
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src/amd/vulkan/radv_shader_info.c
+3 -3
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@@ -449,7 +449,9 @@ gather_shader_info_vs(struct radv_device *device, const nir_shader *nir, const s
info->vs.dynamic_num_verts_per_prim =
pipeline_key->vs.topology == V_008958_DI_PT_NONE && info->is_ngg && nir->xfb_info;
if (info->next_stage == MESA_SHADER_GEOMETRY) {
if (info->next_stage == MESA_SHADER_TESS_CTRL) {
info->vs.as_ls = true;
} else if (info->next_stage == MESA_SHADER_GEOMETRY) {
info->vs.as_es = true;
info->esgs_itemsize = radv_compute_esgs_itemsize(device, info->vs.num_linked_outputs);
}
@@ -1535,8 +1537,6 @@ radv_link_shaders_info(struct radv_device *device, struct radv_pipeline_stage *p
struct radv_pipeline_stage *vs_stage = producer;
struct radv_pipeline_stage *tcs_stage = consumer;
vs_stage->info.vs.as_ls = true;
if (pipeline_key->dynamic_patch_control_points) {
/* Set the workgroup size to the maximum possible value to ensure that compilers don't
* optimize barriers.