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Author SHA1 Message Date
Faith Ekstrand
93acce99f3 vulkan: Default override patch version to VK_HEADER_VERSION 
The patch version shouldn't matter but, on the off chance it does, we
don't want to be advertising non-existent versions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26383>
 2023-11-28 23:52:27 +00:00
Konstantin Seurer
11897376c7 radv/rt: Skip null checks for small case counts 
The individual cases make sure the sbt_idx is not null implicitly
because the handles are always != 0.

Totals from 60 (22.56% of 266) affected shaders:
Instrs: 47841 -> 47655 (-0.39%)
CodeSize: 255028 -> 253460 (-0.61%)
Latency: 1179658 -> 1225311 (+3.87%); split: -0.02%, +3.89%
InvThroughput: 224122 -> 232851 (+3.89%); split: -0.02%, +3.92%
Copies: 12049 -> 12043 (-0.05%); split: -0.37%, +0.32%
Branches: 3312 -> 3290 (-0.66%)
PreSGPRs: 3494 -> 3472 (-0.63%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25089>
 2023-11-28 22:58:35 +00:00
Konstantin Seurer
fe674f67b1 radv/rt: Use a helper for inlining non-recursive stages 
So we don't have to write the same logic multiple times.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25089>
 2023-11-28 22:58:35 +00:00
Sagar Ghuge
3f747fcbfc iris: Init aux map state for compute engine 
We need to write the aux map address during the batch initialization for
compute engine as well otherwise we would run into gpu hang with
compression enabled.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10194

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26342>
 2023-11-28 21:27:59 +00:00
Alyssa Rosenzweig
d5e0901fd5 agx: fix 1D texture sampling 
fixes texwrap 1d bordercolor cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26377>
 2023-11-28 20:32:03 +00:00
Alyssa Rosenzweig
e14633fa7d nir/lower_tex: Add 1D lowering 
From amd/common.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26377>
 2023-11-28 20:32:03 +00:00
Caio Oliveira
5de5a0d475 intel/compiler: Don't use fs_visitor::bld in thread payload classes 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26301>
 2023-11-28 19:53:51 +00:00
Caio Oliveira
2d6240ab14 intel/compiler: Don't use fs_visitor::bld in fs_reg_alloc 
Just set up the builder without relying on the pre-existing one.  Moves
one step close to remove bld from fs_visitor.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26301>
 2023-11-28 19:53:51 +00:00
Caio Oliveira
f55867b56c intel/compiler: Don't use fs_visitor::bld in tests 
Tests create their own fs_builder now.  Moves one step closer to remove
bld from fs_visitor.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26301>
 2023-11-28 19:53:51 +00:00
Caio Oliveira
9540259e1c intel/compiler: Prefer ctor/dtors in some Google Tests 
Per Google Test FAQ recommendation, prefer consutrctors and destructors
unless there's a need to use SetUp/TearDown.

We will take advantage of this later to initialize an fs_builder.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26301>
 2023-11-28 19:53:51 +00:00
José Roberto de Souza
d0db92b52d iris: Check for maximum allowed priority in Xe KMD 
Previous code was settting whatever priority was requested even if
Xe KMD would not allow it causing warnings in dmesg:

xe 0000:00:02.0: [drm:exec_queue_set_priority [xe]] Ioctl argument check failed at drivers/gpu/drm/xe/xe_exec_queue.c:235: value > xe_exec_queue_device_get_max_priority(xe)
xe 0000:00:02.0: [drm:xe_exec_queue_set_property_ioctl [xe]] Ioctl argument check failed at drivers/gpu/drm/xe/xe_exec_queue.c:912: ret

Now it will query the maximum allowed priority and set the priority
closed to what application requested.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26325>
 2023-11-28 18:17:45 +00:00
José Roberto de Souza
6a245e4eea intel: Share function to do device query in Xe KMD 
A "dance" is required with this uAPI, first we need to ask KMD what is
the size of the giving query id, then memory needs to be allocated to
match that size and then query again with the memory address set and
at this time Xe KMD will copy the query data to memory.

This dance was being duplicated in xe_engine_get_info() and
anv_xe_physical_device_get_parameters() and the next patch will also
use it in Iris, so here adding it common/xe and re-using as much
as possible.

There is one more implementation of this function in intel/dev but
due to how libs are linked intel/dev can't depend on to intel/common.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26325>
 2023-11-28 18:17:45 +00:00
Marek Olšák
c5e37e7c39 radeonsi: only expose GL_AMD_performance_monitor on gfx7-10.3 
It's only implemented for those generations.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26262>
 2023-11-28 17:34:26 +00:00
Marek Olšák
c7729effa6 radeonsi: group equal CAP cases 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26262>
 2023-11-28 17:34:26 +00:00
Marek Olšák
7a7285bc69 gallium: add PIPE_CAP_PERFORMANCE_MONITOR for GL_AMD_performance_monitor 
Use a CAP instead of guessing it. radeonsi won't expose it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26262>
 2023-11-28 17:34:26 +00:00
Marek Olšák
6073a149b9 gallium/docs: make CAP doc order match definition order 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26262>
 2023-11-28 17:34:26 +00:00
Christian Gmeiner
0d6803feb0 docs: Update etnaviv extensions 
Next round of feature updates.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26189>
 2023-11-28 16:55:51 +00:00
Raphaël Gallais-Pou
5c92ef9116 gallium: add sti DRM entry point 
stih418-b2264 implements an ARM Mali 400 GPU[1]. Add an entry point for sti
DRM vendor, so mesa can be used with it.

[1]: https://lore.kernel.org/lkml/20230727215141.53910-14-avolmat@me.com

Signed-off-by: Raphaël Gallais-Pou <rgallaispou@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26189>
 2023-11-28 16:55:51 +00:00
Lionel Landwerlin
b18006397b anv: remove heuristic preferring dedicated allocations 
This heuristic doesn't show much difference when you have a beafy
processor but on lower end skus, it increase the number of buffers in
the execbuffer ioctl, adding significant overhead in i915.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4cdd3178fb ("anv: Meet CCS alignment reqs with dedicated allocs")
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26335>
 2023-11-28 16:13:11 +00:00
Lionel Landwerlin
7b87e1afbc anv: track & unbind image aux-tt binding 
This solves a problem when you have a big memory chunk of which some
regions are bound to images. If the image is destroyed, currently the
aux-tt mapping stays and prevent any new image aux-tt mapping within
that region, until the memory is freed.

This maps & unmaps the aux-tt region at respectively bind & destroy
time, so that the memory chunks can be map through aux-tt.

If there is aliasing of memory to 2 different images, then the first
one "wins" the aux mapping and gets compression support. The second
one doesn´t.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ee6e2bc4a3 ("anv: Place images into the aux-map when safe to do so")
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26335>
 2023-11-28 16:13:11 +00:00
Lionel Landwerlin
b09db9d823 anv: use main image address to determine ccs compatibility 
The BO address is not really a good criteria since we can bind an
image at an offset inside a BO.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ee6e2bc4a3 ("anv: Place images into the aux-map when safe to do so")
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26335>
 2023-11-28 16:13:11 +00:00
Lionel Landwerlin
7c6faa1efe intel/aux_map: introduce ref count of L1 entries 
To implement this feature, we need to do CPU side tracking of all
L3/L2/L1 entries. This does add a little bit of CPU allocations, but
the advantage is that the traversal of the page table tree is faster.
No more need for the linear seach of find_buffer().

With this feature, we can have multiple VkImage bind to the same main
memory address, as long as they share exact same mapping parameters.
The AUX mapping will be removed when the last VkImage is destroyed.

As previously, if the L1 mapping entry parameters don't match, the
mapping fails. Anv handles this nicely by just disabling AUX on the
image.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26335>
 2023-11-28 16:13:11 +00:00
Samuel Pitoiset
02ef01fa95 radv: enable DGC preprocessing for IBO 
This seems to improve performance for Starfield by +1% and Halo Infinite
by +15%!

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10025
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
e59a16bbb8 radv: use an indirect draw when IBO isn't updated as part of DGC 
To remove the dependency on the cmd buffer state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
2807e27231 radv: set the stream VA for DGC graphics 
This will be used to emit indirect draws when needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Samuel Pitoiset
88bbdfd23e radv: remove useless NIR instructions when emitting IBO with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
 2023-11-28 14:07:37 +00:00
Lionel Landwerlin
e22e88f8ce intel/fs: reuse set_predicate() 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26306>
 2023-11-28 13:40:07 +00:00
Lionel Landwerlin
83a1657b6c intel/fs: fix incorrect register flag interaction with dynamic interpolator mode 
Once NIR code is lowered and a few optimization passes have run, there
might be flag register interactions between instructions quite far
away from one another.

In the following case :

   f0 = and r0, r1
   ...
   fs_interpolate r2, r3
   ...
   if f0
      ...
   endif

If we lower fs_inteporlate while using the f0 register, we completely
garble the value meant for the if block.

To fix this, emit the predication for fs_interpolate in brw_fs_nir.cpp
when doing the NIR translation to the backend IR. This will guarantee
that the flag register interactions are visible to the optimization
passes, avoiding the problem above.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 68027bd38e ("intel/fs: implement dynamic interpolation mode for dynamic persample shaders")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9757
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26306>
 2023-11-28 13:40:07 +00:00
Georg Lehmann
4b9618ceec aco: add test for post-ra DPP clobbered in linear cfg 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26373>
 2023-11-28 12:48:56 +00:00
Georg Lehmann
576afa8540 aco: don't optimize DPP across more than one block 
Register write tracking doesn't work for inactive lanes, so this was unsafe.

Foz-DB Navi31:
Totals from 8 (0.01% of 78196) affected shaders:
Instrs: 11513 -> 11515 (+0.02%)
CodeSize: 61056 -> 61064 (+0.01%)

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10197
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26373>
 2023-11-28 12:48:56 +00:00
Samuel Pitoiset
06c9e69f44 radv/ci: add new flakes for VEGA10 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26384>
 2023-11-28 09:04:08 +01:00
Jesse Natalie
f843b14c17 d3d12: Fix hevc encoder 32-bit build (uint64_t -> size_t) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26363>
 2023-11-27 21:15:24 +00:00
Jesse Natalie
ae62fc01fa d3d12: Fix h264 encoder 32-bit build (uint64_t -> size_t) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26363>
 2023-11-27 21:15:24 +00:00
Faith Ekstrand
500955b6cb nak: Only insert barriers around ifs if they actually re-converge 
We don't care about patterns like

    loop {
        ...
        if (...) {
            break;
        } else {
            ...
        }
        ...
    }

In that case, we don't need to sync after the if because there's nothing
to re-converge.  Every path except one will end up breaking out of it
anyway.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26382>
 2023-11-27 20:59:34 +00:00
Faith Ekstrand
804201a3d7 nak: Run rustfmt 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26382>
 2023-11-27 20:59:34 +00:00
Faith Ekstrand
e93935dd04 nvk: Limit shader stages to supported stages 
Fixes: c7c73d6d17 ("nvk: Enable subgroups features")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26382>
 2023-11-27 20:59:34 +00:00
Iván Briano
6f9be9a2a0 hasvk: ensure we reapply always pipeline dynamic state in runtime state 
Backport of 24631d308c

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26341>
 2023-11-27 20:36:07 +00:00
Rhys Perry
2d98236dd5 ac/nir: fix partial mesh shader output writes on GFX11 
Fixes dEQP-VK.mesh_shader.ext.smoke.monolithic.mesh_shader_triangle with
nir_opt_combine_stores disabled.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 240e16fc8e ("ac/nir/ngg: Use attribute ring for mesh shader params.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25530>
 2023-11-27 20:11:03 +00:00
Mary Guillemard
f59665bb62 venus: Do not submit batch manually when no feedback is required 
This fixes hangs with Zink on piglit spec@arb_sparse_buffer tests caused by the double submission.

Fixes: a55d26b566 ("venus: add back sparse binding support")

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26375>
 2023-11-27 19:53:09 +00:00
Jesse Natalie
1924cdc289 d3d12: Fix multidimensional array ordering 
Apparently my C multimensional array syntax was rusty.

Fixes: a6740ee7 ("d3d12: Fix indexing of local_reference_state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26362>
 2023-11-27 19:36:16 +00:00
Samuel Pitoiset
da3f3a46b1 ci: uprev vkd3d-proton to 2.11 
This contains many new tests.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26376>
 2023-11-27 15:18:19 +00:00
Eric Engestrom
cf510e38a5 intel/ci: fix .hasvk-manual-rules 
Fixes: 570acf5655 ("ci: Add a manual full and 1/10th hasvk CTS runs.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26259>
 2023-11-27 12:55:18 +00:00
Eric Engestrom
1942073112 intel/perf: fix regex escaping 
`\$` is interpreted before being passed to `re.search()`, but luckily
for us the escape is also invalid and because of that, python 3.12+
warns us about it.

Use a raw string instead, so that the `\` is passed untouched to
`re.search()`.

Fixes: aa04b47c6e ("intel/perf: add support for GtSlice/GtSliceXDualsubsliceY variables")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26355>
 2023-11-27 11:58:03 +00:00
Eric Engestrom
1492d24f89 lp: make sure 0xff is unsigned before shifting it past signed int range 
src/gallium/auxiliary/gallivm/lp_bld_format_s3tc.c:2446:82: runtime error: left shift of 255 by 24 places cannot be represented in type 'int'

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26368>
 2023-11-27 09:51:01 +00:00
Christian Gmeiner
023fa0aa5d etnaviv: Mark etna_rs_gen_clear_surface(..) private 
There are no users outside of etnaviv_rs.c.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26096>
 2023-11-27 06:59:05 +00:00
Christian Gmeiner
9342544ca5 etnaviv: rs: Call etna_rs_gen_clear_surface(..) when needed 
Calling etna_rs_gen_clear_surface(..) during surface creation could end
in the following assert:
   etna_rs_gen_clear_surface: Assertion `!"" "bpp not supported for clear by RS"'

Lets call etna_rs_gen_clear_surface(..) only when it is needed.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26096>
 2023-11-27 06:59:05 +00:00
Pierre-Eric Pelloux-Prayer
945288ffae radeonsi: check sctx->tess_rings is valid before using it 
Fixes: c89ca3b47f ("radeonsi: change si_emit_derived_tess_state into a state atom")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10015

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26190>
 2023-11-25 15:33:03 +00:00
Marek Olšák
b6e98677c3 nir/print: print PATCH0 and VARn_16BIT names instead of numbers for TCS and TES 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26275>
 2023-11-25 09:50:19 -05:00
Marek Olšák
5c8730ebe8 nir: don't declare illegal varyings in nir_create_passthrough_tcs 
I called it accidentally with LAYER.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26275>
 2023-11-25 09:50:19 -05:00
Marek Olšák
7a9b73fcb8 nir: fix gathering TESS_LEVEL_INNER/OUTER usage with lowered IO 
Those varyings shouldn't flag patch_inputs_read/patch_outputs_written.

Fixes: 10be706778 - nir: gather indirect info from lowered IO intrinsics

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26275>
 2023-11-25 09:50:19 -05:00