8b5c800d1f
asahi: use NIR gathered interpolation
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36501 >
2025-08-03 21:57:26 +00:00
e8ff9eb9cb
nir/opt_varyings: link interpolation qualifiers
...
Some hardware (AGX, Imagination, Arm) really want to know the interpolation
qualifiers when compiling the vertex shader. Even though we need to handle this
dynamic for separate shaders, we can improve performance by linking.
nir_opt_varyings already has all the information to do this, so just do so.
Note this has to be done in common code for Gallium, which links varyings within
the GLSL linker but then presents the linked programs as separate shader
objects. This models that nicely, allowing Gallium drivers to optimize without
weird sidebands.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36501 >
2025-08-03 21:57:25 +00:00
66740d9c91
nir: gather interpolation qualifiers
...
we'll want this to be able to link interpolation qualifiers in a simple way with
nir_opt_varyings. add the metadata for it and the FS gathering pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36501 >
2025-08-03 21:57:25 +00:00
b8f50b6317
nir: gather info in opt_varyings_bulk
...
the info is all messed up so we need to do this right after. merge this
code.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36501 >
2025-08-03 21:57:25 +00:00
3e8575c037
nir,agx: pull lower_printf_buffer into backend
...
no other users now.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36516 >
2025-08-03 21:27:50 +00:00
1edd9c3e53
panfrost: don't use nir_lower_printf_buffer
...
it's kind of silly now.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Reviewed-by: John Anthony <john.anthony@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36516 >
2025-08-03 21:27:49 +00:00
1708230415
lvp: replace lower_ray_tracing_stack_base with inline_sysval
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36516 >
2025-08-03 21:27:48 +00:00
a52cdc08b7
pan/bi: replace specialize_idvs with nir_inline_sysval
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Reviewed-by: John Anthony <john.anthony@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36516 >
2025-08-03 21:27:48 +00:00
3719983edf
brw: replace lower_fs_msaa with nir_inline_sysval
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36516 >
2025-08-03 21:27:47 +00:00
1c28fc0a86
nir: add nir_inline_sysval pass
...
a bunch of drivers have versions of this, might as well make a common one.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Reviewed-by: John Anthony <john.anthony@arm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36516 >
2025-08-03 21:27:47 +00:00
3c9471c8d7
people: add John Anthony
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36516 >
2025-08-03 21:27:45 +00:00
3735ac6165
tu: Use nir_opt_reassociate.
...
I've elected to go with the more aggressive CSE heuristic here in addition
to scalar math, which shaves another 1% on instruction count in exchange
for a small hit to max waves. With either CSE or scalar, we take a
notable hit to spilling (STP/LDP) on Aztec Ruins, Civ 6, Fallout 4, and
Monster Hunter World, and with CSE those get worse.
Totals (A750):
MaxWaves: 6803894 -> 6795012 (-0.13%); split: +0.20%, -0.33%
Instrs: 154246248 -> 151508232 (-1.78%); split: -1.92%, +0.15%
CodeSize: 324303600 -> 322969162 (-0.41%); split: -0.84%, +0.43%
NOPs: 24723513 -> 24536554 (-0.76%); split: -3.04%, +2.29%
MOVs: 4729771 -> 4711212 (-0.39%); split: -3.75%, +3.36%
COVs: 1762268 -> 1762432 (+0.01%); split: -0.05%, +0.06%
Full: 4679471 -> 4688316 (+0.19%); split: -0.46%, +0.65%
(ss): 3443963 -> 3450363 (+0.19%); split: -2.33%, +2.51%
(sy): 1811290 -> 1811142 (-0.01%); split: -1.15%, +1.15%
(ss)-stall: 12438303 -> 12597798 (+1.28%); split: -3.17%, +4.45%
(sy)-stall: 47647687 -> 47720784 (+0.15%); split: -1.56%, +1.71%
STPs: 35424 -> 35846 (+1.19%); split: -0.26%, +1.45%
LDPs: 28110 -> 28643 (+1.90%); split: -0.45%, +2.34%
Preamble Instrs: 38170428 -> 39461432 (+3.38%); split: -0.33%, +3.71%
Early Preamble: 355599 -> 355772 (+0.05%); split: +0.16%, -0.11%
Subgroup size: 41463040 -> 41355072 (-0.26%); split: +0.17%, -0.43%
Cat0: 27282700 -> 27094195 (-0.69%); split: -2.77%, +2.08%
Cat1: 6609687 -> 6589640 (-0.30%); split: -2.84%, +2.54%
Cat2: 75455473 -> 72725047 (-3.62%); split: -3.77%, +0.15%
Cat3: 32359423 -> 32526926 (+0.52%); split: -0.35%, +0.87%
Cat4: 4691910 -> 4694398 (+0.05%); split: -0.00%, +0.05%
Cat5: 3316443 -> 3316276 (-0.01%); split: -0.01%, +0.00%
Cat6: 1031600 -> 1032185 (+0.06%); split: -0.03%, +0.09%
Cat7: 3499012 -> 3529565 (+0.87%); split: -2.02%, +2.89%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36342 >
2025-08-03 20:58:28 +00:00
d5826506ce
nir,agx: Move AGX's loop (generalized) to shared NIR code.
...
When I went to use opt_reassociate for tu, I was advised that you want to
do this loop to get the best results. If everyone needs it, let's make it
common code and explain what's going on.
In the process, also make it skip work appropriately when there's no
progress.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36342 >
2025-08-03 20:58:28 +00:00
61bf050bb9
ci/radeonsi: Add a flake on mendocino that appeared yesterday.
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36496 >
2025-08-03 20:27:39 +00:00
3cd6728de4
zink: Lower sample shading before we add_derefs().
...
Otherwise, you'll still get interp_at_centroid even when we had tried to
switch it to sample.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36496 >
2025-08-03 20:27:39 +00:00
062a35b554
nir/lower_sample_shading: Set the sample qualifier on in vars.
...
This is another step in setting things up, that zink would like to have.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36496 >
2025-08-03 20:27:39 +00:00
d3ada77a6a
nir: Move ST's force-persample-shading NIR pass to shared code.
...
This is about to grow a little.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36496 >
2025-08-03 20:27:39 +00:00
c550cfce88
hk: use new reset query kernel
...
this avoids pathologically bad performance for large #s of writes. fixes
extremely bad performance in RDR2.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13603
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:41:11 -04:00
43e0a2d3a5
libagx: port reset query helper to libagx
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:41:11 -04:00
d2cb6ea0e1
libagx: factor out query_report
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:41:11 -04:00
7f8ed2628b
asahi: use 16-bit coordinates for bg program
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:41:11 -04:00
8a8fe2ffc1
agx: handle 16-bit coordinates
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:41:11 -04:00
0319bd0a84
agx: set register cache hints
...
impl cribbed from the Valhall compiler. that seems only fair, I wrote the
code either way (-:
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:54 -04:00
35e70bf30a
agx: lower export even later
...
so we can do reg cache opt as late as possible without losing this information.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:54 -04:00
d9c0971e50
agx: plumb is_alu query for reg cache opt
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:54 -04:00
a27e51f3c1
agx: fix cache bit packing
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:54 -04:00
e97005e688
agx: fix simd reduce forcing no cache bit
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:54 -04:00
c6111cc43c
agx: fix export instructions in the IR
...
so we can see thru them properly.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:54 -04:00
17f2a3af7a
agx: fix reg cache printing
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:54 -04:00
d15bfdf0a7
agx: track block divergence
...
conservative for now. we'll need this for correctness.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:54 -04:00
fc9f3363fa
agx: add foreach_reg_{src,dest}
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
700a88233b
asahi: rename compressed 1 to just compressed
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
74ed2b78e8
asahi,hk: optimize no-op FS
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
626fa80c1b
asahi: optimize pass type with depth-only passes
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
7f2a6cdd26
hk: only enable image view min LOD for dx12
...
I don't really want random Vulkan apps using this. fixes Steam shading
precaching via fossilize.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
a0a18c084e
hk: kill psiz writes via topology, not feature
...
this regresses DXVK fast link shaders, I guess, but fixes Proton shader
precompiles. per discussion with Hans-Kristian
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
9c987ee75e
asahi: use native colour masking
...
seems to work now.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
562377f01d
agx: try to rematerialize to improve occupancy
...
we already have a perfectly good spiller and SSA... use it when it helps. yes,
this costs a bit of CPU time, but it's guarded behind enough checks that the
average time should be fine.
this was prompted by a shadertoy where we were losing waves due to way too
many constants pooled at the start of a chunky shader.
in GL shader-db, only affected shaders are in blender:
instrs HURT: shaders/blender/1020.shader_test FS: 3125 -> 3178 (1.70%)
instrs HURT: shaders/blender/981.shader_test FS: 3125 -> 3178 (1.70%)
instrs HURT: shaders/blender/729.shader_test FS: 3086 -> 3154 (2.20%)
instrs HURT: shaders/blender/1023.shader_test FS: 3085 -> 3153 (2.20%)
instrs HURT: shaders/blender/424.shader_test FS: 3085 -> 3153 (2.20%)
threads helped: shaders/blender/1020.shader_test FS: 576 -> 640 (11.11%)
threads helped: shaders/blender/1023.shader_test FS: 576 -> 640 (11.11%)
threads helped: shaders/blender/424.shader_test FS: 576 -> 640 (11.11%)
threads helped: shaders/blender/729.shader_test FS: 576 -> 640 (11.11%)
threads helped: shaders/blender/981.shader_test FS: 576 -> 640 (11.11%)
in VK fossils, there's a lot more high pressure shaders that benefit:
Totals from 113 (0.21% of 54019) affected shaders:
MaxWaves: 64448 -> 73088 (+13.41%)
Instrs: 388529 -> 391646 (+0.80%); split: -0.00%, +0.80%
CodeSize: 2750064 -> 2769106 (+0.69%); split: -0.00%, +0.69%
ALU: 292960 -> 295863 (+0.99%); split: -0.00%, +0.99%
FSCIB: 292960 -> 295863 (+0.99%); split: -0.00%, +0.99%
GPRs: 21297 -> 19289 (-9.43%)
Preamble instrs: 75703 -> 75911 (+0.27%)
notable improvement in Far Cry 5.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
6544a4f1ae
asahi: drop sink/move in GS code
...
this is asking for trouble, since divergence analysis doesn't handle stuff we
lower quickly. this fixes geometry shaders blowing up since the cited commit,
but since I was the one who r-b'd that change, I don't have anyone to blame but
myself C:
Fixes: d61edf079balyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36399 >
2025-08-03 14:40:53 -04:00
e4584c9470
tu: Add support for realtime vk priority
...
The kernel creates 4 rings so it is possible to map each of vulkan's
priority to each ring.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36172 >
2025-08-03 12:46:17 +00:00
8227283d58
nak: Drop include paths for size_of and size_of_val
...
They have been added to the prelude with Rust 1.80.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36526 >
2025-08-03 10:16:21 +00:00
8376ecd842
rusticl: Use std::mem::offset_of!()
...
Support for nested fields got stabilized with Rust 1.82.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36526 >
2025-08-03 10:16:21 +00:00
0631b4fd7e
rusticl: Drop include paths for size_of, size_of_val, and align_of
...
They have been added to the prelude with Rust 1.80.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36526 >
2025-08-03 10:16:21 +00:00
d4a7811519
rusticl: Use is_aligned from std
...
It got stabilized with Rust 1.79.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36526 >
2025-08-03 10:16:20 +00:00
6c7084357d
mesa: Bump required Rust version to 1.82
...
Firefox ESR requires Rust 1.82 since version 140. Thus, this update
is in line with our Rust update policy.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: Karol Herbst <kherbst@redhat.com >
Reviewed-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36526 >
2025-08-03 10:16:20 +00:00
eda7043025
docs/rusticl: Update documented version requirements for meson and bindgen
...
The requirements bump a few weeks ago forgot to update the docs.
Fixes: 1a698c75aekherbst@redhat.com >
Reviewed-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36526 >
2025-08-03 10:16:20 +00:00
b364732502
ci/rust: Drop date from Rust release channel selection
...
For stable Rust, specifying the patch version already uniquely identifies a toolchain build. Specifying the date would only be required for nightly releases.
Reviewed-by: Eric Engestrom <eric@igalia.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36526 >
2025-08-03 10:16:19 +00:00
b101aecb03
ir3: add shader bisect debug tool
...
When debugging a problem in a trace, CTS test,... that is caused by a
known compiler feature, the first step is usually to find which shader
causes the problem. This is often non-trivial as the amount of shaders
in a trace can be huge. This commit adds a debugging tool to help with
this.
The idea behind this tool is to assign every shader a deterministic
(pre-compilation) ID that can be used to order shaders. Once we have
this, we can use it to bisect which shader causes the problem. This
obviously only works if the problem can be traced back to a single
shader. In my experience, this is often the case.
This tool reuses the shader cache key as deterministic ID. It is
concatenated with the variant ID to distinguish the different variants
of a shader.
In practice, bisecting the shaders in a test run works like this:
- Gate the problematic compiler feature using ir3_shader_bisect_select;
E.g., if (ir3_shader_bisect_select(v)) IR3_PASS(...);
- Run test with IR3_SHADER_BISECT_DUMP_IDS_PATH=ids.txt
- Sort ids.txt
- Bisect the shader IDs using IR3_SHADER_BISECT_LO/IR3_SHADER_BISECT_HI.
- Dump the problematic shader using IR3_SHADER_BISECT_DISASM.
A Python script is provided to make all this easier:
- ir3_shader_bisect.py dump-ids -o ids.txt 'test args'
- ir3_shader_bisect.py bisect -i ids.txt 'test args'
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33602 >
2025-08-03 09:30:49 +00:00
0a123ce68b
ir3: add pointer from ir3_shader_variant to ir3_shader
...
Needed in the next commit to get the shader key for a variant.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33602 >
2025-08-03 09:30:49 +00:00
d36594f7f0
ir3/ra: fix file start wraparound
...
The initial wraparound was calculated in a way I do not fully
understand. However, it could lead to not starting from register 0 when
a wraparound occurs. This, in turn, could lead to some unnecessary gaps.
Fix this by explicitly setting start to 0 when a wraparound occurs.
Totals from 16452 (10.00% of 164575) affected shaders:
Instrs: 16456187 -> 16449330 (-0.04%); split: -0.14%, +0.10%
CodeSize: 32357818 -> 32345432 (-0.04%); split: -0.14%, +0.10%
NOPs: 3411778 -> 3410810 (-0.03%); split: -0.43%, +0.40%
MOVs: 603559 -> 603199 (-0.06%); split: -0.81%, +0.75%
COVs: 262804 -> 262761 (-0.02%); split: -0.13%, +0.11%
Full: 279264 -> 279179 (-0.03%); split: -0.04%, +0.01%
(ss): 422887 -> 422739 (-0.03%); split: -0.81%, +0.77%
(sy): 188298 -> 188513 (+0.11%); split: -0.53%, +0.65%
(ss)-stall: 1685300 -> 1679865 (-0.32%); split: -0.99%, +0.67%
(sy)-stall: 5797450 -> 5788564 (-0.15%); split: -0.74%, +0.58%
STPs: 18359 -> 18341 (-0.10%); split: -0.14%, +0.04%
LDPs: 32825 -> 32833 (+0.02%); split: -0.22%, +0.24%
Preamble Instrs: 3307822 -> 3308388 (+0.02%); split: -0.31%, +0.33%
Early Preamble: 5853 -> 5852 (-0.02%)
Last helper: 4154632 -> 4164580 (+0.24%); split: -0.34%, +0.58%
Cat0: 3760257 -> 3759249 (-0.03%); split: -0.39%, +0.36%
Cat1: 968587 -> 963086 (-0.57%); split: -0.99%, +0.43%
Cat2: 6133128 -> 6133532 (+0.01%); split: -0.03%, +0.03%
Cat6: 183289 -> 183275 (-0.01%); split: -0.05%, +0.05%
Cat7: 684028 -> 683290 (-0.11%); split: -0.35%, +0.25%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36374 >
2025-08-03 08:58:29 +00:00
Alyssa Rosenzweig