brw: replace lower_fs_msaa with nir_inline_sysval
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36516>
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@@ -1528,7 +1528,27 @@ brw_compile_fs(const struct brw_compiler *compiler,
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}
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NIR_PASS(_, nir, brw_nir_move_interpolation_to_top);
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NIR_PASS(_, nir, brw_nir_lower_fs_msaa, key);
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if (!brw_wm_prog_key_is_dynamic(key)) {
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uint32_t f = 0;
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if (key->multisample_fbo == INTEL_ALWAYS)
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f |= INTEL_MSAA_FLAG_MULTISAMPLE_FBO;
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if (key->alpha_to_coverage == INTEL_ALWAYS)
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f |= INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE;
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if (key->provoking_vertex_last == INTEL_ALWAYS)
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f |= INTEL_MSAA_FLAG_PROVOKING_VERTEX_LAST;
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if (key->persample_interp == INTEL_ALWAYS) {
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f |= INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH |
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INTEL_MSAA_FLAG_PERSAMPLE_INTERP;
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}
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NIR_PASS(_, nir, nir_inline_sysval, nir_intrinsic_load_fs_msaa_intel, f);
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}
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brw_postprocess_nir(nir, compiler, debug_enabled,
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key->base.robust_flags);
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@@ -178,8 +178,6 @@ bool brw_nir_lower_cs_intrinsics(nir_shader *nir,
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bool brw_nir_lower_alpha_to_coverage(nir_shader *shader);
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bool brw_needs_vertex_attributes_bypass(const nir_shader *shader);
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void brw_nir_lower_fs_barycentrics(nir_shader *shader);
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bool brw_nir_lower_fs_msaa(nir_shader *shader,
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const struct brw_wm_prog_key *key);
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void brw_nir_lower_vs_inputs(nir_shader *nir);
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void brw_nir_lower_vue_inputs(nir_shader *nir,
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@@ -1,50 +0,0 @@
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/*
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* Copyright (c) 2025 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include "compiler/nir/nir_builder.h"
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#include "brw_nir.h"
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static bool
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brw_nir_lower_fs_msaa_intel_instr(nir_builder *b,
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nir_intrinsic_instr *intrin,
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void *data)
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{
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if (intrin->intrinsic != nir_intrinsic_load_fs_msaa_intel)
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return false;
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b->cursor = nir_before_instr(&intrin->instr);
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const struct brw_wm_prog_key *key = data;
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uint32_t fs_msaa_flags =
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(key->multisample_fbo == INTEL_ALWAYS ?
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INTEL_MSAA_FLAG_MULTISAMPLE_FBO : 0) |
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(key->persample_interp == INTEL_ALWAYS ?
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(INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH |
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INTEL_MSAA_FLAG_PERSAMPLE_INTERP) : 0) |
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(key->alpha_to_coverage == INTEL_ALWAYS ?
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INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE : 0) |
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(key->provoking_vertex_last == INTEL_ALWAYS ?
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INTEL_MSAA_FLAG_PROVOKING_VERTEX_LAST : 0);
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nir_def_replace(&intrin->def, nir_imm_int(b, fs_msaa_flags));
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return true;
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}
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bool
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brw_nir_lower_fs_msaa(nir_shader *shader,
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const struct brw_wm_prog_key *key)
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{
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if (brw_wm_prog_key_is_dynamic(key))
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return false;
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return nir_shader_intrinsics_pass(shader,
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brw_nir_lower_fs_msaa_intel_instr,
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nir_metadata_control_flow |
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nir_metadata_live_defs |
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nir_metadata_divergence,
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(void *)key);
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}
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@@ -73,7 +73,6 @@ libintel_compiler_brw_files = files(
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'brw_nir_lower_cs_intrinsics.c',
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'brw_nir_lower_alpha_to_coverage.c',
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'brw_nir_lower_fs_barycentrics.c',
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'brw_nir_lower_fs_msaa.c',
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'brw_nir_lower_immediate_offsets.c',
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'brw_nir_lower_intersection_shader.c',
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'brw_nir_lower_ray_queries.c',
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