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11905 Commits

Author SHA1 Message Date
Sagar Ghuge 69fc7ee622 intel/disasm: Fix cache load/store disassembly for URB messages 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28868>
 2024-05-09 19:45:18 +00:00
Faith Ekstrand 91b62e9868 anv: Use spirv_capabilities for the float64 shader 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905>
 2024-05-09 01:14:23 +00:00
Faith Ekstrand 9d5b4a4ffd intel/kernel: Use the new capabilities struct 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905>
 2024-05-09 01:14:23 +00:00
Faith Ekstrand ce2946ae0f vulkan: Set SPIR-V caps from supported features 
Any drivers which use vk_spirv_to_nir() now no longer need to build a
caps table manually.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905>
 2024-05-09 01:14:23 +00:00
Faith Ekstrand c1eaa03904 spirv: Drop the SubgroupUniformControlFlow check 
It's just a vtn_fail_if() and there's no actual cap for it.  It's not
really gaining us much to have the check.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905>
 2024-05-09 01:14:22 +00:00
Lionel Landwerlin 28a0f98123 intel/tools: add README file 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27594>
 2024-05-08 22:50:47 +00:00
Tvrtko Ursulin bab52763f4 intel/hang_replay: fix batch address 
Also capture all buffers so that we can compare replay run with the
original error state.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27594>
 2024-05-08 22:50:47 +00:00
Lionel Landwerlin a9f1151de2 intel/hang_replay: use hw image param 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27594>
 2024-05-08 22:50:47 +00:00
Lionel Landwerlin 4d69870071 intel/hang_replay: use newer API of i915 execbuffer 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27594>
 2024-05-08 22:50:47 +00:00
Lionel Landwerlin 665cad6408 anv: fix ycbcr plane indexing with indirect descriptors 
We need to add the plane index to compute the address from which to
load the descriptor (anv_sampled_image_descriptor in this case).

This was likely broken before we added direct descriptor support so
that gets a stable backport.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11125
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29111>
 2024-05-08 21:51:49 +00:00
Tapani Pälli c225f89d34 anv: skip gfx push constants alloc optimization on gfx9/11 
Always reallocate in cmd_buffer_flush_gfx_push_constants like was done
before the the optimization got introduced.

Fixes: 62d96a6546 ("anv: add dirty tracking for push constant data")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11064
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28999>
 2024-05-08 17:21:26 +00:00
José Roberto de Souza 73188a4590 intel/perf: Add function to open perf stream 
This will make easy to add Xe KMD support and reduce code duplication.
No changes in behavior are expected here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
José Roberto de Souza d27dcb815e intel/perf: Add and use a function to return platform OA format 
The platform version check to return the OA format was duplicated
in a few places, so adding a function and dropping this duplication.

While at it, already making it future proof for Xe KMD support and
split i915 specific code to its own file.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
José Roberto de Souza 137021fbe0 hasvk: Free intel_perf_config when destroying physical device 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
José Roberto de Souza a941ce746a anv: Free intel_perf_config when destroying physical device 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
José Roberto de Souza 4b179e7bea intel/ds: Nuke ralloc_ctx and ralloc_cfg 
Now that perf config and context are freed we don't need this rallocs
contexts.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
José Roberto de Souza 6c3ebff569 intel/ds: Free perf config and context 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
José Roberto de Souza 2cecf3e8a8 intel/perf: Add intel_perf_free_context() 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
José Roberto de Souza ebe8d2f9ea intel/perf: Add intel_perf_free() 
There was no function to free resources allocated in intel_perf_config
or it self.
Other callers will be added in separated patches.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
José Roberto de Souza a9a53c914d intel/perf: Store pointer intel_device_info to in intel_perf_config 
This will reduce host memory usage a bit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077>
 2024-05-07 21:44:34 +00:00
Oskar Viljasaar 2d575034f2 hasvk: switch to use runtime physical device properties infrastructure 
Remove the GPDP and GPDP2 entrypoints, and fill the properties
at device initialization time instead.
Move DRM master major/minor gathering before get_properties() and WSI
init, as the latter uses the results gathered by the former.

Reviewed-by: Julia Tatz <tatz.j@northeastern.edu>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27717>
 2024-05-07 08:45:18 +00:00
Oskar Viljasaar 55967a411d anv: Move completely over to common runtime GetPhysicalDeviceProperties2 
The runtime grew support for VkPhysicalDevicePresentationPropertiesANDROID,
so we can use that now and get rid of anv_GetPhysicalDeviceProperties2.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27717>
 2024-05-07 08:45:17 +00:00
Lionel Landwerlin 8c1cc405d3 anv: VK_EXT_legacy_vertex_attributes 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29070>
 2024-05-07 08:16:20 +03:00
Sagar Ghuge e32828f5fc intel/compiler: Fix destination type for CMP/CMPN 
For CMP/CMPN, use src0 type if destination is null otherwise get the
src0 type register with destination register size.

This fixes dEQP-VK.glsl.builtin_var.frontfacing.* tests cases on Xe2+.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28679>
 2024-05-06 21:46:18 +00:00
Lionel Landwerlin 610a7c84c3 anv: move empty_vs_input to physical device 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057>
 2024-05-06 09:20:01 +00:00
Lionel Landwerlin 725397759a anv: move device initialization as the last step of vkCreateDevice 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057>
 2024-05-06 09:20:01 +00:00
Lionel Landwerlin 63c4d24f7d anv: avoid requirement to put flush_data as first field 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057>
 2024-05-06 09:20:01 +00:00
Lionel Landwerlin ae6d20815a anv: fix leak of custom border colors 
Inside a HAVE_VALGRIND section.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4dad2a4a6f ("anv: enable shader border color capture/replay")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057>
 2024-05-06 09:20:01 +00:00
Lionel Landwerlin e260b16b11 anv: fixup alloc failure handling in reserved_array_pool 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 806281f61f ("anv: add a new reserved pool for capture/release")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057>
 2024-05-06 09:20:01 +00:00
Ian Romanick 0fa17962d6 intel/elk: Fix optimize_extract_to_float for i2f of unsigned extract 
Fixes fs-uint-to-float-of-extract-int8.shader_test and
fs-uint-to-float-of-extract-int16.shader_test added by piglit!883.

v2: Expand the comment explaining the potential problem. Suggested by
Caio.

Fixes: e6022281f2 ("intel/elk: Rename files to use elk prefix")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27891>
 2024-05-03 15:01:43 -07:00
Ian Romanick fc2360167c intel/brw: Avoid optimize_extract_to_float when it will just be undone later 
v2: Add bspec quotation. Suggested by Caio. With better understand of
the restriction, only apply on DG2 and newer platforms.

shader-db:

DG2 and Meteor Lake had similar results. (DG2 shown)
total instructions in shared programs: 19659363 -> 19659360 (<.01%)
instructions in affected programs: 2484 -> 2481 (-0.12%)
helped: 6 / HURT: 1

total cycles in shared programs: 823445738 -> 823432524 (<.01%)
cycles in affected programs: 2619836 -> 2606622 (-0.50%)
helped: 48 / HURT: 63

fossil-db:

DG2 and Meteor Lake had similar results. (DG2 shown)

Totals:
Instrs: 154015863 -> 153987806 (-0.02%); split: -0.02%, +0.00%
Cycle count: 17552172994 -> 17562047866 (+0.06%); split: -0.13%, +0.19%
Spill count: 142124 -> 141544 (-0.41%); split: -0.54%, +0.13%
Fill count: 266803 -> 266046 (-0.28%); split: -0.38%, +0.09%
Scratch Memory Size: 10266624 -> 10271744 (+0.05%); split: -0.02%, +0.07%
Max live registers: 32592428 -> 32592393 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 5535944 -> 5535912 (-0.00%); split: +0.00%, -0.00%

Totals from 41887 (6.63% of 631367) affected shaders:
Instrs: 32971032 -> 32942975 (-0.09%); split: -0.10%, +0.01%
Cycle count: 3892086217 -> 3901961089 (+0.25%); split: -0.60%, +0.85%
Spill count: 105669 -> 105089 (-0.55%); split: -0.72%, +0.18%
Fill count: 206459 -> 205702 (-0.37%); split: -0.49%, +0.12%
Scratch Memory Size: 7766016 -> 7771136 (+0.07%); split: -0.03%, +0.09%
Max live registers: 3230515 -> 3230480 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 337232 -> 337200 (-0.01%); split: +0.00%, -0.01%

No shader-db or fossil-db changes on any earlier Intel platforms.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27891>
 2024-05-03 15:01:43 -07:00
Ian Romanick bf5d82654a intel/brw: Fix optimize_extract_to_float for i2f of unsigned extract 
Fixes fs-uint-to-float-of-extract-int8.shader_test and
fs-uint-to-float-of-extract-int16.shader_test added by piglit!883.

No shader-db or fossil-db changes on any Intel platform.

v2: Expand the comment explaining the potential problem. Suggested by
Caio.

Fixes: 29ce110be6 ("i965/fs: Remove extract virtual opcodes.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27891>
 2024-05-03 15:01:43 -07:00
Kenneth Graunke 8d983b3425 intel/nir: Set src_type on TCS quads workaround store_output 
We weren't setting this and now it's validated, causing assert failures.

Fixes: 1632948a76 ("nir: validate src_type of store_output intrinsics, require bit_size >= 16")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11107
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29027>
 2024-05-02 13:58:21 -07:00
Sviatoslav Peleshko 39c4de7e42 anv: Fix descriptor sampler offsets assignment 
This seems to be a simple copy-paste mistake. It makes sense to or-assign
surface offsets because we clear the actual offset part with a mask first,
but sampler offsets should be just assigned instead.

Fixes: 7c76125d ("anv: use 2 different buffers for surfaces/samplers in descriptor sets")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10790
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29019>
 2024-05-02 14:49:37 +00:00
José Roberto de Souza be518657b9 intel/perf: Change oa_format to uint64_t 
Xe KMD will not provide a enum with formats, instead UMD needs set
a uint64_t with type, counter_sel, counter_size and bc_report for the
format.

So here changing from int to uint64_t, it do not causes any issues for
i915 and makes it ready for Xe KMD.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28997>
 2024-05-02 14:25:41 +00:00
José Roberto de Souza 9cb4ff9b0e intel/perf: Fix the error check of i915_add_config() 
i915_add_config() returns 0 for error or a positive integer for success
but callers were checking for a negative number for errors.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28997>
 2024-05-02 14:25:41 +00:00
José Roberto de Souza a56dc30ba6 intel/perf: Remove i915_drm.h include from gen_perf.py 
The generated file don't use any symbol in i915_drm.h

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28997>
 2024-05-02 14:25:40 +00:00
José Roberto de Souza 14b890c797 intel/perf: Nuke platform_supported 
Only set, never used.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28997>
 2024-05-02 14:25:40 +00:00
Rohan Garg e50234de86 anv: allocate space for generated indirect draw id's using the temporary allocation helper 
Generated Indirect Draw's need a small temporary allocate to store draw
id's. Use the new temporary allocation helper to allocate that space.

Fixes: 82d772fa9b ("anv: create new helper for small allocations")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28989>
 2024-05-02 08:32:09 +00:00
Iván Briano a24ed1146d anv: consolidate DestroyPipeline for graphics and graphics_lib 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29011>
 2024-05-01 21:07:28 +00:00
Iván Briano 6223388c73 anv: fix casting to graphics_pipeline_base 
The macro takes the type of the pipeline to check for, but the cast to
base checks for a full graphics pipeline, so if used on a library one it
fails.

Cc: mesa-stable

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29011>
 2024-05-01 21:07:28 +00:00
Kenneth Graunke 84139470a5 intel/brw: Use VEC for emit_unzip() 
Helps make SIMD-split code more SSA-friendly.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:54 -07:00
Kenneth Graunke 1b54b4fad5 intel/brw: Use VEC for NIR vec*() sources 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:50 -07:00
Kenneth Graunke d4563747d9 intel/brw: Use VEC for output stores 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:49 -07:00
Kenneth Graunke f0c29c9b71 intel/brw: Use VEC for FS outputs 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:49 -07:00
Kenneth Graunke cbe7a13f2b intel/brw: Use VEC for TCS/TES/GS input/output loads 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:48 -07:00
Kenneth Graunke a94e1bd0ac intel/brw: Use VEC for gl_FragCoord 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:47 -07:00
Kenneth Graunke d0a24496fd intel/brw: Use VEC for load_const 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:45 -07:00
Kenneth Graunke 3c867bf2c7 intel/brw: Add a new VEC() helper. 
This gathers a number of sources into a contiguous vector register.
Eventually, the plan is that it will use a MOV for a single source,
or LOAD_PAYLOAD for multiple sources.  For now, it emits a series of
MOVs to allow us to rewrite a bunch of existing code to use the new
helper, then change them all over at once later.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:42 -07:00
Kenneth Graunke c194df565a intel/brw: Don't include unnecessary undefined values in texture results 
When emitting a sampler message, we allocate a temporary destination
large enough to hold 4 values (or 5 for sparse).  This is the maximum
size needed to hold any result.  However, we shrink the size written by
the sampler message to skip writing any trailing components that NIR
tells us are never read.  So we may not write the entire temporary.

The NIR texture instruction has a destination VGRF which is sized
assuming that all components are present.  We issue a LOAD_PAYLOAD
instruction to copy our sampler result temporary to the NIR destination.
When we reduce the response length of the sampler messages, then some of
these temporary components have undefined values.  The correct way to
indicate that is by using a BAD_FILE source.  Unfortunately, we were
naively reading offsets of the temporary that were never written, but
are still part of a larger VGRF.  This complicates things.

For example, sampling and only using RGB (not RGBA) was producing this:

   txl_logical(8) (written: 3) vgrf3+0.0:F, ...
   undef(8) (written: 4) vgrf4:UD
   load_payload(8) (written: 4) vgrf4:F, vgrf3+0.0:F, vgrf3+1.0:F, vgrf3+2.0:F, vgrf3+3.0:F

The last source, vgrf3+3.0:F, is undefined, and should be BAD_FILE.
Doing so allows VGRF splitting and other optimizations to work better.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:41 -07:00