8a3e85776a
glsl_types: derive ht
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28056 >
2024-03-12 19:41:50 +00:00
c29110ef99
v3d: derive ht
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28056 >
2024-03-12 19:41:49 +00:00
2d32239b7a
radeonsi: derive ht
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28056 >
2024-03-12 19:41:49 +00:00
3f287d100c
nvk: derive ht
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28056 >
2024-03-12 19:41:49 +00:00
da59672e2b
asahi: derive ht
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28056 >
2024-03-12 19:41:49 +00:00
be5c288dbf
panfrost: derive ht
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28056 >
2024-03-12 19:41:49 +00:00
93879b1920
util/hash_table: add DERIVE macro
...
we typically use a hash table with a fixed struct key, but this requires tedious
boilerplate. add a macro that generates all the boilerplate for you so you can
just create a table and go.
naming inspired by Rust #![derive].
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28056 >
2024-03-12 19:41:49 +00:00
49a89911c4
nir/print: do not print empty lists on intrinsics
...
before:
32 %0 = @load_vertex_id () ()
after:
32 %0 = @load_vertex_id
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com >
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27925 >
2024-03-12 19:00:26 +00:00
ec9b6b5cfa
util: add _mesa_hash_table_u64_num_entries
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27925 >
2024-03-12 19:00:26 +00:00
a6123a80da
nir/opt_shrink_vectors: shrink some intrinsics from start
...
If the backend supports it, intrinsics with a component() are straightforward to
shrink from the start. Notably helps vectorized I/O.
v2: add an option for this and enable only on grown up backends, because some
backends ignore the component() parameter.
RADV GFX11:
Totals from 921 (1.16% of 79439) affected shaders:
Instrs: 616558 -> 615529 (-0.17%); split: -0.30%, +0.14%
CodeSize: 3099864 -> 3095632 (-0.14%); split: -0.25%, +0.11%
Latency: 2177075 -> 2160966 (-0.74%); split: -0.79%, +0.05%
InvThroughput: 299997 -> 298664 (-0.44%); split: -0.47%, +0.02%
VClause: 16343 -> 16395 (+0.32%); split: -0.01%, +0.32%
SClause: 10715 -> 10714 (-0.01%)
Copies: 24736 -> 24701 (-0.14%); split: -0.37%, +0.23%
PreVGPRs: 30179 -> 30173 (-0.02%)
VALU: 353472 -> 353439 (-0.01%); split: -0.03%, +0.02%
SALU: 40323 -> 40322 (-0.00%)
VMEM: 25353 -> 25352 (-0.00%)
AGX:
total instructions in shared programs: 2038217 -> 2038049 (<.01%)
instructions in affected programs: 10249 -> 10081 (-1.64%)
total alu in shared programs: 1593094 -> 1592939 (<.01%)
alu in affected programs: 7145 -> 6990 (-2.17%)
total fscib in shared programs: 1589254 -> 1589102 (<.01%)
fscib in affected programs: 7217 -> 7065 (-2.11%)
total bytes in shared programs: 13975666 -> 13974722 (<.01%)
bytes in affected programs: 65942 -> 64998 (-1.43%)
total regs in shared programs: 592758 -> 591187 (-0.27%)
regs in affected programs: 6936 -> 5365 (-22.65%)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev > (v1)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28004 >
2024-03-12 18:17:17 +00:00
aa99753a28
nir/opt_shrink_vectors: hoist alu helpers
...
to be used earlier in the file in the next commit
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28004 >
2024-03-12 18:17:17 +00:00
d1916432ab
intel/dev: Nuke display_ver
...
It is not used.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28128 >
2024-03-12 17:44:46 +00:00
b09ffe48f2
intel/dev: Nuke 'ver == 10' check
...
There is no intel_device_info with ver 10 anymore.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28128 >
2024-03-12 17:44:46 +00:00
a977a51a21
radv: stop using 5/8 component SSBO stores
...
These apparently work, but I'm not sure they were supposed to.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28108 >
2024-03-12 17:23:29 +00:00
cc7e3efc7c
radv: don't advertise DGC with LLVM
...
The meta shaders for this feature don't compile with LLVM because of 5/8
component SSBO stores. I'm not sure this was ever expected to work.
This seemed to break vkd3d-proton.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28108 >
2024-03-12 17:23:29 +00:00
3409c60099
etnaviv: isa: Support multiple encodings for texldb
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
20678b9204
etnaviv: isa: Fix #instruction-tex-src0-src1-src2 bitset
...
src1 got wrong values.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
ccc99bd42d
etnaviv: isa: Support multiple encodings for texldl
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
8d117b46ea
etnaviv: isa: Support unary texkill instruction
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
86de104d07
etnaviv: isa: Support unary branch instruction
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
0aa737018e
etnaviv: isa: Combine branch and branch_if
...
As we want to use the new asm as a drop-in replacement we
need to combine branch and branch_if back to one bitset.
This is caused by the fact that we need to replicate the defines
in isa.xml.h.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
48e1589b44
etnaviv: isa: Correct #instruction-alu-no-dst-has-src0-src1 expr name
...
This expression only checks if src0 and src1 are in use.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
10a7cf3121
etnaviv: isa: Correct #instruction-alu-no-dst-maybe-src1-src2 name
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
dfb2fcf652
etnaviv: isa: Correct #instruction-cf-src1-src2 bitset name
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
c2ffc7a09b
etnaviv: isa: Correct SRC0_AMODE
...
It is 3 bit long and not one.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
b1cbd35bb5
etnaviv: isa: Move {TEX_SWIZ}
...
Should have never been there.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
d8f6de7314
etnaviv: isa: Add movar opcode
...
I was unable to grab this opcode from blob, so lets just
document it as the Gallium driver makes use of it.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
e77fbe2bcc
etnaviv: isa: Add internal register group
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
f416bb3f8c
etnaviv: isa: Rename reg_group u2 to u
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
cf3fa2fd8c
etnaviv: isa: Reorder instructions
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
9c6378abec
etnaviv: isa: Add div opcode
...
Encoded instruction is taken from blob running the following CL kernel:
__kernel void simple(__global float *out, __global float *in)
{
int iGID = get_global_id(0);
out[iGID] = 4.5f / in[iGID];
}
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
e2a9bc73f5
etnaviv: isa: Remove note about GC3000
...
All the encoded instructions in the Opcodes test are comming
from blob running on different GPU models.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
fa3d2bc486
etnaviv: isa: Add texldd opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.shaders.texture_functions.texturegrad.sampler2d_float_vertex
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
0701f3ef9b
etnaviv: isa: Add texldl opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.shaders.texture_functions.texturegrad.isampler2d_vertex
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
8c86bd0209
etnaviv: isa: Add texldb opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.texture.mipmap.2d.bias.linear_nearest
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
3c72596ebf
etnaviv: isa: Add bit_rev opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.int_lowp_vertex
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
2e2a0e8059
etnaviv: isa: Add movai opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.shaders.struct.uniform.dynamic_loop_struct_array_fragment
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
73584cf46a
etnaviv: isa: Name cond enum value 22
...
Blob told me about it when running:
- dEQP-GLES3.functional.ubo.random.scalar_types.4
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:44 +00:00
20022f5389
etnaviv: isa: Add branch_any opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic.bvec3_api_int_both
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:43 +00:00
6a71636179
etnaviv: isa: Correct dp2 opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES2.functional.shaders.operator.geometric.refract.highp_vec2_float_vertex
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:43 +00:00
47106e0f80
etnaviv: isa: Add bit_extract opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.int_lowp_vertex
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:43 +00:00
3b4cbbf0d2
etnaviv: isa: Add norm_dp2, norm_dp3 and norm_dp4 opcodes
...
Encoded instructions are taken from blob running:
- dEQP-GLES2.functional.shaders.operator.geometric.normalize.mediump_vec2_vertex
- dEQP-GLES2.functional.shaders.operator.geometric.normalize.mediump_vec3_vertex
- dEQP-GLES2.functional.shaders.operator.geometric.normalize.mediump_vec4_vertex
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:43 +00:00
4cd779af3f
etnaviv: isa: Add frc opcode
...
Encoded instruction is taken from blob running:
- dEQP-GLES2.functional.shaders.operator.common_functions.fract.mediump_vec4_vertex
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:43 +00:00
ede0008c16
etnaviv: isa: Add dsx and dsy opcodes
...
Encoded instructions are taken from blob running:
- dEQP-GLES3.functional.shaders.derivate.dfdx.texture.basic.float_highp
- dEQP-GLES3.functional.shaders.derivate.dfdy.texture.basic.float_highp
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:43 +00:00
031c2c26df
etnaviv: isa: Remove duplicate #instruction-alu-atomic
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871 >
2024-03-12 17:02:43 +00:00
0f66589c2a
mesa: force rendertarget usage on required-renderable formats
...
the existing guesswork during format selection for teximage is
accurate most of the time, but it's not accurate all of the time.
GL/ES each have a set of sized formats that are required to be
color renderable, and so any time one of these is allocated as a
texture, it MUST have the rendertarget usage bit attached so that
it can later be bound as a framebuffer attachment
an alternative might be to relax this and then try to do migration
to a different format/buffer later if necessary, but that's hard and
probably not actually as useful
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28055 >
2024-03-12 14:22:17 +00:00
d7def3ccdf
panfrost: add pan_force_afbc_packing driconf
...
This is useful for forcing AFBC-P to be used in applications where it's
know to work well. This can significantly reduce memory consumption and
bandwidth, leading more applications working in the first place, and
also better performance.
Acked-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27916 >
2024-03-12 12:44:49 +00:00
2bcdc4939c
panfrost: add driconf infrastructure
...
This is the boiler-plate code needed to support driver-specific driconf
variables in Panfrost.
Acked-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27916 >
2024-03-12 12:44:49 +00:00
d861bd1563
panfrost: give afbc-packing its own flag
...
There's no point in querying this over and over again for each
resource, especially not when this test is about to become more
complicated. So let's give this its own flag.
Acked-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27916 >
2024-03-12 12:44:49 +00:00
7487ac2046
rusticl/device: support query_memory_info to retrieve available memory
...
Some drivers implement query_memory_info, but not the MAX_GLOBAL_SIZE
compute cap.
Long term we should drop the compute cap anyway.
Signed-off-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28122 >
2024-03-12 12:24:31 +00:00
Alyssa Rosenzweig