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Author SHA1 Message Date
Alyssa Rosenzweig 68a7fafe2a panfrost,panvk: Use dev->has_afbc instead of quirks 
This uses the new property for AFBC we've added. The AFBC quirk is
applied only to v4, and we only set dev->has_afbc on v5+ so this is not
a regression. It now respects the hardware-specific AFBC disable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13497>
 2021-10-22 19:33:38 -04:00
Alyssa Rosenzweig 3e168b97cc panfrost: Detect implementations support AFBC 
AFBC is an optional feature on Bifrost. If it is missing, a bit will be
set in the poorly named AFBC_FEATURES register. Check this so we can act
appropriately.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13497>
 2021-10-22 19:33:38 -04:00
Emma Anholt ebe9494b61 turnip: Drop the assertion about the temporary bit in sync fd imports. 
Khronos's conclusion was that you only need the bit when you want
temporary and there's a choice between temporary and permanent.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13473>
 2021-10-22 21:44:44 +00:00
Emma Anholt 8ccf672fa3 gallium/u_blitter: Read MSAA z/s from sampler's .x instead of .y or .z. 
u_format defines depth formats as having depth in .x, mesa/st samples for
depth or stencil in .x (not making use of any other channels).
util_make_fs_blit_zs() looks for depth or stencil in .x.  The MSAA path
was the exception looking for it in .z or .y, which was causing drivers to
need to splat their values out to the other channels.  This should be
better on hardware that can emit shorter messages for sampling just the
first channels.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13446>
 2021-10-22 18:31:20 +00:00
Paulo Zanoni 785dd68599 iris: also dump bo's imported and exported flags 
My original patch also aligned the columns for better printing, but
Ken's recent suballocation series incorporated those changes. My
original patch was also printing the EXEC_OBJECT_ASYNC flag, but this
is not possible anymore as we don't have the validation list here. But
it's fine since EXEC_OBJECT_ASYNC is conditional on
iris_bo_is_external(), which is true for either exported or imported.

Example output:

BO list (length 13):
[ 0]:   8 (  8) command buffer @ 0xfffffffefffdd000 (system    65536B)  2 refs
[ 1]:   1 (  1) workaround     @ 0xfffffffefffff000 (system     4096B)  3 refs
[ 2]:  14 ( 14) dynamic state  @ 0x00000002fffef000 (system    65536B)  2 refs  write
[ 3]:   0 ( 10) miptree        @ 0xfffffffeffc00000 (system   471104B)  4 refs  write
[ 4]:  15 ( 15) shader kernels @ 0x00000000ffff7000 (system    16384B)  2 refs
[ 5]:   0 ( 13) buffer         @ 0xfffffffefe700000 (system  1048576B)  2 refs
[ 6]:   4 (  4) surface state  @ 0x00000001fffef000 (system    65536B)  2 refs
[ 7]:   3 (  3) binder         @ 0x0000000100000000 (system    65536B)  2 refs
[ 8]:  18 ( 18) miptree        @ 0xfffffffeffebd000 (system   524288B)  2 refs  write exported
[ 9]:  11 ( 11) buffer         @ 0xfffffffefe800000 (system 20971520B)  2 refs
[10]:   0 ( 13) buffer         @ 0xfffffffefe600000 (system  1048576B)  2 refs
[11]:  12 ( 12) shader kernels @ 0x00000000ffffb000 (system    16384B)  2 refs
[12]:   5 (  5) buffer         @ 0xfffffffeffffe000 (system     4096B)  2 refs  write

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12654>
 2021-10-22 16:54:42 +00:00
Marek Olšák 520300ad22 st/mesa: don't crash when draw indirect buffer has no storage 
Fixes: 22f6624ed3 - gallium: separate indirect stuff from pipe_draw_info

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13471>
 2021-10-22 16:25:28 +00:00
Matt Turner 2822b1345c tu: Expose required VK_FORMAT_FEATURE bits for planar YUV formats 
Specifically this enables these VK_FORMAT_FEATURE bits:

  VK_FORMAT_FEATURE_TRANSFER_SRC_BIT
  VK_FORMAT_FEATURE_TRANSFER_DST_BIT
  VK_FORMAT_FEATURE_SAMPLED_IMAGE_YCBCR_CONVERSION_LINEAR_FILTER_BIT
  VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT
  VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT
  VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT
  VK_FORMAT_FEATURE_MIDPOINT_CHROMA_SAMPLES_BIT
  VK_FORMAT_FEATURE_COSITED_CHROMA_SAMPLES_BIT

Fixes the following tests:
  dEQP-VK.api.info.format_properties.g8_b8_r8_3plane_420_unorm
  dEQP-VK.api.info.format_properties.g8_b8r8_2plane_420_unorm
  dEQP-VK.api.info.image_format_properties.2d.optimal.g8_b8_r8_3plane_420_unorm
  dEQP-VK.api.info.image_format_properties.2d.optimal.g8_b8r8_2plane_420_unorm

Additionally allows 339 tests in dEQP-VK.ycbcr.* to go from Skip to
Pass.

[ Connor: Fake support for 3-plane formats, fixup modifiers path ]

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6792>
 2021-10-22 11:25:31 +00:00
Jonathan Marek 330a8cfa07 turnip: enable UBWC for NV12 
Use the special format for accessing the Y plane of UBWC-enabled NV12, and
enable UBWC for NV12.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6792>
 2021-10-22 11:25:30 +00:00
Connor Abbott 9c895e133b tu: Emit GRAS_LRZ_MRT_BUF_INFO_0 
The blob seems to always emit this, even though it seems to only be used
when rendering to the special planar formats (which we only do in the
blit path). Based on the LRZ prefix it might used in other cases though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6792>
 2021-10-22 11:25:30 +00:00
Connor Abbott c135c2cdb7 freedreno/a6xx: Rename GRAS_2D_BLIT_INFO 
It's not actually used for 2d blits, it's supposed to mirror
RB_MRT_BUF_INFO[0].COLOR_FORMAT and seems to be used only when rendering
to the special planar formats, although the blob name seems to suggest
it's connected to LRZ.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6792>
 2021-10-22 11:25:30 +00:00
Jonathan Marek 8ea6f17fdf freedreno/layout: Fix the UBWC block size for the Y plane 
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6792>
 2021-10-22 11:25:30 +00:00
Matt Turner e0a74c7cad util/format: Add PIPE_FORMAT_Y8_UNORM as an "other" layout format 
freedreno has a different layout for tiled Y8 planes from normal R8
textures, so we need to be able to talk about them separately.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6792>
 2021-10-22 11:25:30 +00:00
Iago Toral Quiroga ceaf56920c v3dv: refactor TFU jobs 
We had an implementation for image copies and another for buffer to
image copies. Refactor the code so we have a single implementation
of this.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13481>
 2021-10-22 11:05:33 +00:00
Tapani Pälli 1465ec8cf3 iris: clear bos_written when resetting a batch 
This fixes dEQP-EGL.functional.sharing.gles2.multithread.* tests that
are hitting: "iris: Failed to submit batchbuffer: Invalid argument"
error.

v2: clear on reset rather than clear 'on-the-fly' (Kenneth Graunke)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5537
Fixes: e4c3d3efc7 ("iris: Defer construction of the validation (exec_object2) list")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13464>
 2021-10-22 09:37:50 +00:00
Samuel Pitoiset b6a69dbb40 radv: re-emit prolog inputs when the nontrivial divisors state changed 
If the application first uses nontrivial divisors, the driver emits
the vertex shader VA to the upload BO rather than directly via the
user SGPRs locations. But, if the vertex input dynamic state changes,
the driver might select a different VS prolog that no longer needs
nontrivial divisors.

In this case, the driver needs to re-emit the prolog inputs because
otherwise the VS prolog will jump to the PC that is emitted via the
user SGPR locations, and the previous one was somewhere in the
upload BO...

This fixes a GPU hang with Bioshock and Zink.

Fixes: d9c7a17542 ("radv: enable VK_EXT_vertex_input_dynamic_state")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13377>
 2021-10-22 09:47:50 +02:00
Samuel Pitoiset 8ec6824335 radv,aco: decouple shader_info/options from radv_shader_args 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13287>
 2021-10-22 07:10:40 +00:00
Kenneth Graunke 1429feaf29 crocus: Replace devinfo->ver[x10] checks with GFX_VER[x10] 
These files are compiled per-generation, so we can just use the #define
instead of the actual field dereference to allow the compiler to dead
code eliminate whole paths.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13475>
 2021-10-22 06:19:15 +00:00
Iago Toral Quiroga 1561d0126a broadcom/compiler: fix assert that current instruction must be in current block 
This was not considering the possibility that the driver has called
nir_before_block() or nir_after_block() to update the cursor, in which
case the cursor link points to the instruction list header and not
to an actual instruction.

Fixes incorrect debug-assert crash in:
dEQP-VK.graphicsfuzz.cov-increment-vector-component-with-matrix-copy

Fixes: 265515fa62 ("broadcom/compiler: check instruction belongs to current block")
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13467>
 2021-10-22 05:39:05 +00:00
Kenneth Graunke e79e1ca304 intel: Drop Tigerlake revision 0 workarounds 
Tigerlake revision 0 is an early stepping that should not be used in
production anywhere, so this code was only used for hardware bringup.
We can drop the unnecessary workarounds.  This also keeps them from
triggering on early steppings of other Gfx12 parts.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13266>
 2021-10-21 16:53:43 -07:00
Marek Olšák 6ef192bddf mesa: discard draws with count=0 to decrease overhead 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13445>
 2021-10-21 21:16:13 +00:00
Nanley Chery 7daff157bb iris: Refactor the assignment to possible_usages 
* Make the outer if-ladder dependent on the has_* variables.
* Make the possible_usages assignments happen at the same nesting level.
* Move the combined HIZ/MCS assert closer to relevant if-else blocks.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11960>
 2021-10-21 20:21:26 +00:00
Nanley Chery 114f87c1c7 iris: Set DISABLE_AUX_BIT for AUX_USAGE_NONE modifiers 
This avoids unnecessary surface padding on TGL+.

Also, drop some of the logic to handle modifiers in
iris_resource_configure_aux as the bit now causes it to be handled
implicitly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11960>
 2021-10-21 20:21:26 +00:00
Nanley Chery b9d8793646 iris: Disable the MC_CCS modifier with norbc 
We generally try to disable CCS whenever the norbc debug flag is set.
Also, this enables simplifying iris_resource_configure_aux later on.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11960>
 2021-10-21 20:21:26 +00:00
Nanley Chery b71264e465 iris: Convert some mod_info checks to asserts 
Depth and multisample images aren't supported with modifiers. So,
instead of checking for the absence of modifiers before adding HiZ or
MCS, simply assert that they aren't present at a more convenient time.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11960>
 2021-10-21 20:21:26 +00:00
Rob Clark 138be96301 freedreno/ir3: Fix validation of subgroup macros 
They don't need to enforce that src types are all the same.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark e68d918ffb freedreno/ir3: Get req_local_mem from pipe_compute_state 
mesa/st initializes req_local_mem to shader->info.shared_size.  But for
clover the shared size doesn't come from the shader.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f58438320c freedreno/ir3: Add ihadd/uhadd 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f5ce806ed7 freedreno/ir3: Add wide load/store lowering 
Lower load/store for vectors wider than 4.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 7a7ac8cd40 freedreno/ir3: Fix reg size validation 
8b types also live in half-regs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 8a6934dfe8 freedreno/ir3: Fix load/store_global_ir3 type 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 81eefe0090 freedreno/ir3: 8bit fixes 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f7b2d613c5 freedreno/ir3: 16b bools 
A create_immed_for_instr() type thing could be useful to make the immed
type match other src(s) for instruction..

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 9a2562a545 freedreno/ir3: Deal with zero-source instructions 
Needed by the next patch, which starts treating bools as 16bit exposing
a bug that was previously accidentially hidden for instructions like
ELECT_MACRO.  Needed for next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark b6e11225a2 freedreno: Fix set_global_binding 
The gallium interface is a bit awkward, but pointer sizes are actually
64b despite what the API suggests.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 0a35ba5c43 freedreno/ir3: Move lower_idiv_options 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark e544a9db16 freedreno/ir3: Add support for load_kernel_input 
Used for function arguments to compute kernels (ie. OpenCL).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark e10c76d277 freedreno/ir3: implement load_work_dim intrinsic 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 3bd265a393 freedreno/ir3: vec8+vec16 support 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f5bbf77be8 freedreno: implement set_compute_state() 
This interface should really go away, but for now just implement it
to directly update constant state (ie. what clover *should* be doing
instead)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 1e9f27f37f freedreno/ir3: Handle MESA_SHADER_KERNEL 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 83a1bca952 freedreno: Skip built-in shaders for clover 
Avoids assert:

  ../src/compiler/glsl_types.cpp:1134: static const glsl_type *glsl_type::get_array_instance(const glsl_type *, unsigned int, unsigned int): Assertion `glsl_type_users > 0' failed.

caused by us trying to compile built-in shaders (ie. clear, gmem<->mem,
etc) before clover has initialized glsl_types.  But we don't need these
shaders for compute-only contexts.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev dff8a0c4cb isaspec: inherite parent's bitset gpu gen requirements 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark d77b9fb518 isaspec: Fix gpu_id for default_options 
We forgot to set this.  It starts to matter in the next patch, otherwise
pre-pass to detect branch targets (needed for backwards jumps/branches)
will not work.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev c4e7541b9d freedreno/ir3: use stg.a/ldg.a only if offset is reg or doesn't fit 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 064c806d23 freedreno/ir3: Add load/store_global lowering 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev d85eb9268a freedreno/ir3: set proper dst size for {store,load}_{global,shared}_ir3 
We want to pass 64b variables.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev 1ef43a0be7 freedreno/ir3: disallow immediate addr/offset for ldg/ldg.a 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark f45b7c58c4 freedreno/ir3: Lower 64b phis 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Danylo Piliaiev bee9212efb ir3/freedreno: add 64b undef lowering 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00
Rob Clark 2d65e6f56d freedreno/ir3: 64b intrinsic lowering 
Both for OpenCL and VK_KHR_buffer_device_address

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300>
 2021-10-21 18:59:57 +00:00