45ecfcd637
isl: Add func isl_surf_get_tile_info()
2016-01-27 15:12:42 -08:00
9f954310e8
vtn: Fix atan2 for non-scalars.
...
The if/then/else block was bogus, as it can only take a scalar
condition, and we need to select component-wise. The GLSL IR
implementation of atan2 handles this by looping over components,
but I decided to try and do it vector-wise, and messed up.
For now, just bcsel. It means that we do the atan1 math even if
all components hit the quick case, but it works, and presumably
at least one component will hit the expensive path anyway.
2016-01-27 15:07:42 -08:00
f92a35d831
vtn: Fix Modf.
...
We were botching this for negative numbers - floor of a negative rounds
the wrong way. Additionally, both results are supposed to retain the
sign of the original.
To fix this, just take the abs of both values, then put the sign back.
There's probably a better way to do this, but this works for now.
2016-01-27 14:21:08 -08:00
4acfc9effb
i965: Fix SIN/COS precision problems.
...
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
2016-01-27 13:56:54 -08:00
b833e7a63c
anv: Put back code to grow shader scratch space
...
This was lost in commit a71e614d33
2016-01-27 11:36:56 -08:00
38a3a535eb
anv: Update the device limits.
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Fixes dEQP-VK.api.info.device.properties. I haven't tested any others.
2016-01-26 23:09:45 -08:00
d3607351fe
gen7/cmd_buffer: SCISSOR_RECT structs are tightly packed
...
The pointer has to be 32-byte aligned, but the structs themselves are 2
dwords each, tightly packed.
2016-01-26 22:10:14 -08:00
f2f03c5b65
anv/pipeline: Set MaximumVPIndex in 3DSTATE_CLIP
2016-01-26 21:52:59 -08:00
dc3de6f8df
anv/pipeline: Only lower input indirects if EmitNoIndirectInput is set
2016-01-26 21:45:21 -08:00
9ac624751e
anv/formats: Use is_power_of_two instead of is_rgb to determine renderability
2016-01-26 20:29:16 -08:00
2af3acd061
HACK/i965/surface_formats: Mark A4B4G4R4 as being supported
...
The table has this marked as unsupported on all gens, but I don't really
believe that given how early it is in the table. I've tested and it seems
to work on Broadwell. The Bspec says that it sould be renderable on SKL+
but alpha blending is questionable.
Side note: We really need to audit the format table again.
2016-01-26 20:29:16 -08:00
c20f78dc5d
anv: Support swizzled formats.
...
Some formats require a swizzle in order to map them to actual hardware
formats. This allows us to turn on two new Vulkan formats.
2016-01-26 20:29:16 -08:00
9bc72a9213
anv/image: Do swizzle remapping in anv_image.c
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TODO: At some point, we really need to make an image_view_init_info that's
a flyweight and stop stuffing everything into image_view.
2016-01-26 20:23:59 -08:00
7d84fe9b1f
HACK: Expose support for stencil blits
...
If someone actually tries to use them, they won't work, but at least we
don't fail to return format properties now.
2016-01-26 17:29:49 -08:00
32dcfc953e
vtn: Delete references to IMix opcode.
...
This is being removed in SPIR-V.
Bugzilla: https://cvs.khronos.org/bugzilla/show_bug.cgi?id=15452
2016-01-26 17:02:35 -08:00
c5dc6cdf26
i965/skl: Utilize new 5th bit for gateway messages
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Cc: Jordan Justen <jordan.l.justen@intel.com >
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com >
2016-01-26 15:44:48 -08:00
a1ea45b857
genX/pipeline: Don't make vertex bindings with holes
2016-01-26 15:44:18 -08:00
7ef0d39cb2
anv/cmd_buffer: Put base_instance in the second component
2016-01-26 15:44:02 -08:00
6840cc1513
anv/image: clflush surface state map in anv_fill_buffer_surface_state().
...
Some of its users had the required clflush on non-LLC platforms, some
didn't. Put the clflush in anv_fill_buffer_surface_state() so we
don't forget.
2016-01-26 15:14:50 -08:00
fc7a7b31c5
anv/image: clflush the right state map in anv_fill_image_surface_state().
...
It was clflushing the nonrt_surface_state structure regardless of
which state structure was actually being initialized.
2016-01-26 15:14:50 -08:00
a50dc70e21
anv/image: Upload raw buffer surface state for untyped storage image and texel buffer access.
2016-01-26 15:14:50 -08:00
d2ec510dda
anv/image: Fix image parameter initialization.
2016-01-26 15:14:50 -08:00
d9e0b9a06a
isl/gen9: Fix slice offset calculation for 1D array images.
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The X component of the offset is set to the layer index times layer
height which is obviously bogus, return the vertical offset of the
slice as Y component instead. Fixes a few image load/store tests that
use 1D arrays on SKL when forcing it to fall back to untyped reads and
writes.
2016-01-26 15:14:50 -08:00
cc065e0ad7
i965/fs_surface_builder: Mask signed integers after conversion
2016-01-26 15:14:50 -08:00
ba393c9d81
anv/image: Actually fill out brw_image_param structs
2016-01-26 15:14:50 -08:00
aa9987a395
anv/image_view: Add base mip and base layer fields
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These will be needed by image_load_store
2016-01-26 15:14:50 -08:00
42cd994177
gen7: Add support for base vertex/instance
2016-01-26 14:56:37 -08:00
4bf3cadb66
gen8: Add support for base vertex/instance
2016-01-26 14:56:37 -08:00
6ba67795db
nir/spirv: Add proper support for InstanceIndex
2016-01-26 14:56:37 -08:00
1c3b7fe1ee
nir/lower_io: Lower INSTNACE_INDEX
2016-01-26 14:56:37 -08:00
b2b7c93318
glsl/enums: Add an enum for Vulkan instance index
2016-01-26 14:56:37 -08:00
da75492879
genX/pipeline: Break emit_vertex_input out into common code
...
It's mostly the same and contains some non-trivial logic, so it really
should be shared. Also, we're about to make some modifications here that
we would really like to share.
2016-01-26 14:56:37 -08:00
fe6ccb6031
anv: Remove long unused anv_aub.h
2016-01-26 14:53:00 -08:00
074a7c7d7c
anv: Dirty fragment shader descriptors in meta restore
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We need to reemit render targets, so dirtying VK_SHADER_STAGE_VERTEX_BIT
doesn't help us much.
2016-01-26 14:44:02 -08:00
725d969753
anv: Reemit STATE_BASE_ADDRESS after second level cmd buffers
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Otherwise the primary batch will continue using the state base addresses
set by the secondary. Fixes remaining renderpass tests.
2016-01-26 14:44:02 -08:00
df5f6d824b
anv/meta: Fix sample mask in clear pipelines
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Once we begin emitting the correct sample mask,
genX_3DSTATE_SAMPLE_MASK_pack will hit an assertion if the mask contains
too many bits.
2016-01-26 11:04:44 -08:00
725fb3623f
i965/compiler: Set nir_options.vertex_id_zero_based
2016-01-25 16:10:28 -08:00
6b6a8a99f8
HACK/i965: Default to scalar GS on BDW+
2016-01-25 15:52:53 -08:00
e462d4d815
Merge remote-tracking branch 'mattst88/nir-lower-pack-unpack' into vulkan
2016-01-25 15:50:31 -08:00
6bbf3814dc
gen7/state: Apply min/mag filters individually for samplers
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This fixes tests which apply different min and mag filters, and depend on
the min filter to be correct.
2016-01-25 15:33:08 -08:00
9c69f4632d
gen8/state: Apply min/mag filters individually for samplers
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This fixes tests which apply different min and mag filters, and depend on the
min filter to be correct.
2016-01-25 15:29:18 -08:00
2434ceabf4
i965/fs: Feel free to spill partial reads/writes
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Now that we properly handle write-masking, this should be safe.
2016-01-25 15:23:10 -08:00
9c0109a1f6
i965/fs: Properly write-mask spills
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For unspills (scratch reads), we can just set WE_all all the time because
we always unspill into a new GRF. For spills, we have two options: If the
instruction has a 32-bit-per-channel destination and "normal" regioning,
then we just do a regular write and it will interleave channels from
different control-flow paths properly. If, on the other hand, the the
regioning is non-normal, then we have to unspill, run the instruction, and
spill afterwards. In this second case, we need to do the spill with
we_ALL.
2016-01-25 15:23:10 -08:00
8e07f7942e
anv: Remove a few finished finishme
2016-01-25 15:16:13 -08:00
76c096f0e7
anv: Remove stale assert
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This goes back to when we didn't have the subpass number in the command
buffer begin info.
2016-01-25 15:15:59 -08:00
874ede4983
i965/gen7+: Use NIR for lowering of pack/unpack opcodes.
2016-01-25 14:48:34 -08:00
5deba3f00a
i965/vec4: Implement nir_op_pack_uvec2_to_uint.
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And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced
by lowering pack[SU]norm4x8 which the vec4 backend does not need.
2016-01-25 14:24:07 -08:00
8bb22dc351
nir: Add lowering support for unpacking opcodes.
2016-01-25 14:24:07 -08:00
d7781038f5
nir: Add lowering support for packing opcodes.
2016-01-25 14:24:07 -08:00
6c1b3bc950
i965/fs: Implement support for extract_word.
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The vec4 backend will lower it.
2016-01-25 14:24:07 -08:00
Chad Versace