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Author SHA1 Message Date
Yonggang Luo 23a2b83639 lavapipe: fixes indent of function lvp_inline_uniforms 
The indent fixes are in separate patch is for easier to review

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:07 +00:00
Yonggang Luo b4ed366d6b lavapipe: Convert to use nir_foreach_function_impl 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:07 +00:00
Yonggang Luo d557169e81 zink: Convert to use nir_foreach_function_impl when possible 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:07 +00:00
Yonggang Luo c7672f4fa5 freedreno: Switch to use nir_foreach_function_impl in tu_shader.cc 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:07 +00:00
Yonggang Luo d45f846946 lima: Convert to use nir_foreach_function_impl when possible 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24316>
 2023-07-25 12:09:06 +00:00
Antonio Gomes 29f4e7b215 rusticl/core: Make convert_spirv_to_nir output pair (KernelInfo, NirShader) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes 2448bdc81b rusticl/core: Delete KernelDevState and KernelDevStateInner 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes 58979e9247 rusticl/program: New helper functions to NirKernelBuild 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes 323dcbb4b5 rusticl: Move NirKernelBuild to ProgramDevBuild 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes 7ec9b9cd07 rusticl/compiler: Remove unnecessary functions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes 218dce5e38 rusticl: Move Cso to Program 
Commit got huge, but couldn't figure out a better way to split without
breaking stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes 11729e8311 rusticl/compiler: Add NirPrintfInfo 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes e3169f624d rusticl/kernel: Add CsoWrapper 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
Antonio Gomes 07c8bce24d rusticl/kernel: Removing unnecessary clone in kernel launch 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23898>
 2023-07-25 10:30:11 +00:00
David Heidelberg f49bfb1108 ci/freedreno: add a530 flake vs-lessthanequal-uvec4-uvec4 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24314>
 2023-07-25 09:26:12 +00:00
Illia Polishchuk c1a02c0138 state_tracker: fix dereference before null check 
Coverity error
CID 1528178 (#1 of 1): Dereference before null check (REVERSE_INULL)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Polishchuk 34e47b40e6 glx: fix dead code when gc var cannot be null due to earlier check 
CID 1528170 (#1 of 1): Logically dead code (DEADCODE)
At condition gc, the value of gc cannot be NULL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Polishchuk c2724b4d37 s/Intel: fix/anv: fix: potentially overflowing expression in genX 
CID 1528164 (#1 of 1): Unintentional integer overflow (OVERFLOW_BEFORE_WIDEN)
overflow_before_widen: Potentially overflowing expression
pool->n_passes * pool->khr_perf_preamble_stride with type
unsigned int (32 bits, unsigned) is evaluated using 32-bit arithmetic,
and then used in a context that expects an expression of type uint64_t (64 bits, unsigned).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Polishchuk 1cbf10ca88 iris: remove NULL check for already dereferenced pointer earlier 
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>

Found by Coverity.

CID: 1528158
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Abernikhin 33546705b5 i915: change format in dbg string 
Actually, uintptr_t is of type unsigned long, but the
debug line uses the %d format specifier, which expects an int.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Abernikhin <illia.abernikhin@globallogic.com>

Found by Coverity.

CID: 1515961
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Illia Abernikhin c22961571a state_tracker: moving initialisation of whandle out from if statement 
whandle initialization inside if statement but used also outside

Signed-off-by: Illia Abernikhin <illia.abernikhin@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Found by Coverity.

CID: 1516746
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20893>
 2023-07-25 08:55:56 +00:00
Konstantin Seurer ae18247e88 lavapipe: Advertise samplerYcbcrConversion 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer 32403c696b lavapipe: Implement samplerYcbcrConversion 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer 2667da5174 lavapipe: Fix binding immutable samplers with desc buffers 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer da95f64a6f lavapipe: Store immutable_samplers as lvp_sampler array 
We will need this to access the ycbcr conversion.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer 7dc6c4b581 lavapipe: Remove dummy sampler ycbcr conversion 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer dbbd84ce8b gallivm: Ignore nir_tex_src_plane 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer c7914a84e9 gallivm: Fix subsampled format sampling under Vulkan 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Konstantin Seurer 1280cf5b2a draw: Do not restart the primitive_id at 0 
Otherwise the primitive_id will wrap around to 0 if more than 4096
patches are drawn.

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24295>
 2023-07-25 08:22:27 +00:00
Samuel Pitoiset df98dca7ad radv: pass submit info to radv_check_gpu_hangs() 
This will allow to dump preambles/postambles CS and eventually even
more CS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24191>
 2023-07-25 06:50:33 +00:00
Samuel Pitoiset 9c95a74e5e radv/amdgpu: rename old_ib to ib in radv_amdgpu_winsys_cs_dump() 
Forgot this variable when I renamed the ib_buffers array.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24191>
 2023-07-25 06:50:33 +00:00
Samuel Pitoiset 7eb1105829 radv/amdgpu: fix dumping CS with the chained IBs path 
ib_buffer is now NULL in both paths, and the first IB is the beginning
of the chain.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24191>
 2023-07-25 06:50:33 +00:00
Samuel Pitoiset 7f173d1ff3 radv: use next_stage for determining the stage to lower NGG 
If the next stage is FS, it's also the last VGT API stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset 340f74e468 radv: simplify getting next VS stage for VS prologs 
It's the VS shader info stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset ca520c49f5 radv: determine as_ls earlier by using the next stage 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset f68316d78b radv: determine ES info for VS/TES with GS earlier 
By using the next stage, it's possible to compute these information
earlier without having to link shaders info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset 4098e47ab6 radv: use the number of GS linked inputs to compute the ESGS itemsize 
It's similar.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset 7c2d38f4d1 radv: add a helper to compute the ESGS itemsize 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Samuel Pitoiset 54ab7b24a2 radv: remove the pipeline dependency for creating a GS copy shader 
This is unnecessary. While we are at it, stop passing the array of
shaders and use the GS stage only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
 2023-07-25 06:31:08 +00:00
Jianxun Zhang 75452f611e intel/common: Only set op mask on instructions in decoder 
When a default value of a struct's field, which is in the
higher half of the first dword, is specified in a gen xml
file, setting op mask makes decoder treat the field as a
header (intel_field_is_header()). As a result, it won't
output the field in batch dump. This is not a common case
but can happen once a gen xml file includes such fields.

The op mask is only meaningful to instructions, so we fix
the above issue by not setting op mask of structs (also
registers).

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24268>
 2023-07-24 22:56:59 +00:00
Nanley Chery 046bba0be0 iris: Handle clear color compatibility in prepare_render 
Before this patch, iris_resource_render_aux_usage would disable
compression when the clear color did not support format
reinterpretation.

With this patch, iris now replaces the clear color with zero and keeps
compression enabled. Disabling fast clears would be enough for most aux
usages, but replacement is also done to handle ISL_AUX_USAGE_FCV_CCS_E.

Note that this also fixes a bug. Format reinterpretation with
incompatible clear colors previously was not handled for the MCS aux
usages.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23676>
 2023-07-24 22:29:01 +00:00
Nanley Chery 1aa4e6bac0 iris: Create BLORP surfaces after resource preparation 
iris_resource_prepare_render will soon gain the ability to change a
resource's clear color. iris_blorp_surf_for_resource will keep a copy of
that clear color, so make sure calls to it happen after the render
preparation helper. At the moment, this shouldn't have an impact besides
improving debugging.

While we're here, do the same for the generic access preparation helper.
We may convert those to more specific helpers at a later time.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23676>
 2023-07-24 22:29:01 +00:00
Nanley Chery 215b50ace1 iris: Pass the render format to prepare_render 
This will be used in an upcoming patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23676>
 2023-07-24 22:29:01 +00:00
Nanley Chery c59ba8ac07 iris: Reorder render_aux_usage parameters 
Match the order of the parameters for iris_resource_texture_aux_usage.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23676>
 2023-07-24 22:29:01 +00:00
Nanley Chery 1d12b29b3f intel/blorp: Ambiguate after CCS resolves on gfx7-8 
ISL's state-machine of CCS_D describes full resolves as leaving the aux
buffer in the pass-through state. Hardware doesn't behave this way on
gfx8 however. On that platform, full resolves transition the aux buffer
to the resolved state. This was verified by dumping the CCS before and
after a full resolve on BDW (gfx7 is simply assumed to behave the same).
Ambiguate after resolving to match driver expectations.

Prevents iris from failing piglit's fcc-write-after-clear on BDW with a
future patch which relies on fast-clear encodings being removed after a
resolve. The avoided failure is:

   Testing implicit read of partial block UNORM -> SNORM
   Probe color at (0,1,0)
     Expected:  1.000000 1.000000 1.000000 1.000000
     Observed:  0.000000 0.000000 0.000000 0.000000

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23676>
 2023-07-24 22:29:01 +00:00
Lionel Landwerlin 8cbf730145 intel/fs: don't try to rebuild sequences of non ssa values 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 04777171e0 ("intel/fs: try to rematerialize surface computation code")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9378
Reviewed-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24228>
 2023-07-24 20:04:24 +00:00
Caio Oliveira 2f3230a736 meson: Ensure that LLVMSPIRVLib is not required for Clover 
Fixes: cb588d5d6e ("compiler/clc: Move related NIR passes to the common mesa clc")
Closes: #9391
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24244>
 2023-07-24 18:21:11 +00:00
Emma Anholt 61ec26db26 ci/tgl: Improve the info for ANGLE's MSAA regression on TGL. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24200>
 2023-07-24 16:07:28 +00:00
Emma Anholt 3ef07e6c44 ci: Uprev ANGLE to 0518a3ff4d4e ("Android: Simplify power metrics collection") 
There have been some fixes for our drivers that we'd like to bring in.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24200>
 2023-07-24 16:07:28 +00:00
Emma Anholt 48b725279e ci/radv: Clarify when the ANGLE GS failures started happening. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24200>
 2023-07-24 16:07:28 +00:00