Commit Graph

210989 Commits

Author SHA1 Message Date
Lionel Landwerlin 3362b8dcb5 brw: use a scalar builder for the load_payload on transpose loads
I noticed SIMD32 shaders have that kind of pattern :

mov(32)         g94<1>D         0D                              { align1 WE_all };
send(1)         g15UD           g94UD           nullUD          0x6210d500                0x02010000
                ugm MsgDesc: ( load, a32, d32, V16, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti )  BTI 2  base_offset 16  { align1 WE_all 1N I@5 $1 };

Why use a 32 wide register for a SEND that is only going to read the first lane?

We can stick a single physical register and reduce register pressure.

DG2 fossils-db results :

Totals:
Instrs: 157417515 -> 157417796 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15362185116 -> 15363086774 (+0.01%); split: -0.05%, +0.05%
Max live registers: 29059141 -> 29051166 (-0.03%)
Max dispatch width: 5071256 -> 5075720 (+0.09%); split: +0.33%, -0.24%

Totals from 82132 (14.43% of 569221) affected shaders:
Instrs: 26564632 -> 26564913 (+0.00%); split: -0.00%, +0.00%
Cycle count: 4630907475 -> 4631809133 (+0.02%); split: -0.16%, +0.18%
Max live registers: 5425037 -> 5417062 (-0.15%)
Max dispatch width: 128384 -> 132848 (+3.48%); split: +12.92%, -9.45%

LNL fossils-db results :

Totals:
Instrs: 141870413 -> 141870745 (+0.00%); split: -0.00%, +0.00%
Cycle count: 20176018818 -> 20191262632 (+0.08%); split: -0.07%, +0.14%
Max live registers: 44858167 -> 44838370 (-0.04%)

Totals from 51859 (10.55% of 491590) affected shaders:
Instrs: 16834547 -> 16834879 (+0.00%); split: -0.00%, +0.00%
Cycle count: 5761980106 -> 5777223920 (+0.26%); split: -0.24%, +0.50%
Max live registers: 5893878 -> 5874081 (-0.34%)

Perf A/B testing only reported a 0.5% improvement on DG2 on one trace, no changes on BMG.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36958>
2025-08-26 12:03:22 +00:00
Lionel Landwerlin 27c69acb6a brw: remove uniform from opt_offsets
Those are for push constants, no point in doing that because :
   - there is no HW constant offsets in push constants (payload
     delivery), it's just register offset calculation
   - if we have an dynamic value it's already using MOV_INDIRECT

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e103afe7be ("brw: run the nir_opt_offsets pass and set the maximum offset size")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36958>
2025-08-26 12:03:22 +00:00
Brais Solla ae7f9552be r300: Added support for GL_ATI_meminfo and GL_NVX_gpu_memory_info
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36859>
2025-08-26 11:47:18 +00:00
Danylo Piliaiev 8faf76a754 tu/a6xx: Fix unaligned buffer_to_image on close to (1 << 14) width
I'm not sure why exactly it didn't work because
TPL1_A2D_SRC_TEXTURE_SIZE seemingly has (1 << 15) width
limit. However tests have shown that it doesn't work out.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36939>
2025-08-26 10:56:13 +00:00
Danylo Piliaiev a288b77403 tu: Fix unaligned image_to_buffer on close to (1 << 14) width
The bottom right corner of the copy exceeded the maximum allowed
value in GRAS_A2D_DEST_BR.x

In order to fix this, we have to do a second copy per line of
the last texels.

Fixes asserts in:
 dEQP-GLES31.functional.copy_image.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36939>
2025-08-26 10:56:13 +00:00
Eric Engestrom 2e33098162 docs/ci: always build the docs
It only takes 2 min of runner time, and it's been broken several times
by now, so let's just always run this job.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36893>
2025-08-26 09:49:56 +00:00
Eric Engestrom a569a5f9c6 docs/ci: drop unnecessary comment
None of the other `rules:` say this, because everyone know this by now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36893>
2025-08-26 09:49:56 +00:00
Eric Engestrom 1b7dd64977 docs/ci: drop redundant/dead fork rule
`.common-rules` already covers that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36893>
2025-08-26 09:49:55 +00:00
Job Noorman 51fa8ad748 freedreno/drm-shim: disable VM_BIND
Turnip crashes under drm-shim when enabling VM_BIND. We don't care about
VM_BIND for shader compilation so just disable it.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 4efbfa1441 ("tu/drm: Enable VM_BIND")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37000>
2025-08-26 09:09:48 +00:00
Eric Engestrom a033cfaa66 broadcom/ci: add ci-tron variant of the piglit traces job
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854>
2025-08-26 08:38:10 +00:00
Eric Engestrom 3ce27c08b4 piglit/ci: configure ci-tron to download traces and upload renders
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854>
2025-08-26 08:38:10 +00:00
Eric Engestrom 137ccdbc54 ci-tron: avoid uploading downloaded traces
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854>
2025-08-26 08:38:10 +00:00
Eric Engestrom 24f5f5037b ci-tron: move s3_jwt token file to the project dir
CI-tron only passes that folder to the dut, not the rest of the system;
this allows CI-tron jobs to upload things to s3.fd.o, like piglit traces
failed renders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854>
2025-08-26 08:38:09 +00:00
Eric Engestrom 9ae98a081b broadcom/ci: drop unnecessary variables redefinitions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36854>
2025-08-26 08:38:09 +00:00
Samuel Pitoiset 944e26eae7 radv: fix hashing graphics pipeline when no stages are compiled
It's possible with GPL.

This fixes a NULL pointer dereference with updated pipeline binaries
tests in VKCTS.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36999>
2025-08-26 07:37:40 +00:00
Karol Herbst b9f060438f nak: rework scale argument of compute_mat and rename it
"scale" was a bad name as it meant nothing others could comprehend.
However that value corresponded to the tile size of the Matrix layouts.
For int8 we have a tile size of 4, for 16 and 32 bit values we have a size
of 2.

For the future the same value need to be 32 for booleans, 8 for int4, 1
for fp64 and tf32 and 4 for all em types.

The "scale = 1 << scale;" assignment can simply be removed because it was
4 for 2 and 2 for 1 simply being the expected value after this change.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36391>
2025-08-26 09:06:51 +02:00
Georg Lehmann d0f4b535fe nir: constant fold txd with 0 ddx/ddy to txl
Foz-DB GFX1201:
Totals from 34 (0.04% of 80287) affected shaders:
Instrs: 3111158 -> 3111076 (-0.00%)
CodeSize: 16345020 -> 16344908 (-0.00%); split: -0.00%, +0.00%
Latency: 15378053 -> 15378063 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 2940485 -> 2940477 (-0.00%); split: -0.00%, +0.00%
VClause: 79940 -> 79941 (+0.00%)
Copies: 228205 -> 228159 (-0.02%)
VALU: 1730040 -> 1729994 (-0.00%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36967>
2025-08-26 06:19:43 +00:00
Arseny Kapoulkine bb3727ce5a ac/rgp: Warn when RGP capture can't be saved without libelf
Without this, mesa build on some distros may silently produce a version
of radv that silently refuses to save RGP traces

Signed-off-by: Arseny Kapoulkine <arseny.kapoulkine@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36960>
2025-08-26 00:42:16 +00:00
Mark Collins 098521559d freedreno/drm: Only initialize memory data source when Perfetto is active
FdMemoryDataSource was being registered as a Perfetto data source
unconditionally which led to anything calling fd_device_new(...)
attempting to do this even when they might not have Perfetto
initialized which is done as a part of util_perfetto_init, without
which trying to register the event causes a SEGFAULT.

Fixes: c7045e3e63 ("perfetto: unify init")

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36993>
2025-08-25 22:04:45 +00:00
Connor Abbott 7d925dbc52 freedreno/ci: Update a750 expectations
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:58 +00:00
Martin Roukala (né Peres) 44dbf8756e freedreno/ci: uprev the kernel for the a750
We are still in the process of moving our kernels to gfx-ci/linux, but
we got the request to uprev the kernel a month ago when I started my
holiday, so let's not delay it more. Anyway, it is better to change
only one variable at a time so no harm done.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:58 +00:00
Connor Abbott d921225af1 freedreno/ci: Update kernel with VM_BIND fixes
Pull in msm-fixes plus a few extra fixes we've accumulated from the
list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:58 +00:00
Connor Abbott 96513b5e8e freedreno/ci: Skip dEQP-VK.memory.mapping.*.full.variable.*
These use too much memory with VM_BIND and aren't super useful. We have
to skip them even with the full jobs to avoid taking them out.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:58 +00:00
Connor Abbott 938ac2b67d freedreno/ci: Add sparse-related a618 skips
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:58 +00:00
Connor Abbott 4d2c14847f tu: Support sparseResidencyAliased
UCHE and CCU use virtual-tagged addresses, so whenever an alias may have
changed we have to always flush and invalidate everything. We detect
this through the sparse memory aliasing flag on the buffer/image, or for
plain memory barriers whether the feature is enabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott 8feed47fce tu: Initial support for sparse binding
Plumb through support for a sparse queue and enable sparse binding using
the kernel interfaces we added earlier. We also support sparse residency
for buffers, which is straightforward, but sparse residency for images
is much more complicated so it will be enabled later.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott 71ef46717c tu/kgsl: Add support for sparse binding
Use the "virtual BO" interface.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott 797c74452f tu/drm: Add support for sparse binding
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott f9daddf5d5 tu/knl: Add an API for sparse binding
Add a "sparse VMA" abstraction, and functions creating them, destroying
them, and submitting commands to map and unmap BOs into them. This
mirrors the Vulkan API, but with image offsets resolved to page offsets.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott 4efbfa1441 tu/drm: Enable VM_BIND
Use a new driver-internal VM_BIND submit queue for mapping and unmapping
"normal" BOs. This will be required for sparse, because we can't mix
the old and new interface, but it should also allow us to stop using
"zombie" VMAs and the bo list.

Also use MSM_BO_NO_SHARE, which we assume is available when VM_BIND is.
This should significantly reduce kernel submit overhead, in parallel to
the userspace submit overhead cut by using VM_BIND.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott 460ed35916 tu: Fix CmdBindTransformFeedbackBuffersEXT size handling
According to the spec and as implemented by other drivers, this should
use the size of the buffer instead of the size of the VkDeviceMemory
it's bound to when VK_WHOLE_SIZE is specified or pSizes is NULL. The
current behavior doesn't make sense at all for sparse buffers which are
not bound to a single VkDeviceMemory. Just use the common helper that
already does the right thing, copied from anv.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott aa392e1ec2 tu: Align BO size to page size
The kernel was rounding the size up for us, but it doesn't like a
non-aligned map size, so just sanitize the size here.

tu_cs was relying on the size not being rounded to keep the maximum size
2^20-1 or less, so fix that by using the initial unrounded size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott d8d0e73899 freedreno/drm: Import new UABI for VM_BIND
Imported from kernel commit 203dcde88156
("Merge tag 'drm-msm-next-2025-07-05' of https://gitlab.freedesktop.org/drm/msm into drm-next").

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Connor Abbott 51a7aebc86 tu: Refactor BO deletion
For VM_BIND, BO deletion will have to be implemented differently in
native drm and virtio. We already have a somewhat awkward situation with
native-specific code in the common BO deletion helper, which we only get
away with because it's for kernels without SET_IOVA in which case virtio
isn't supported. Add a few common helpers for some of the guts, and move
the guts into backend-specific functions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32533>
2025-08-25 20:11:57 +00:00
Christian Gmeiner e689b342fe etnaviv: Optimize sampler view iteration with u_foreach_bit(..)
Replace loop over all PIPE_MAX_SAMPLERS with u_foreach_bit(..) to iterate
only over active sampler views. This avoids unnecessary iterations.

Improves drawoverhead test 1 performance by ~10%.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36831>
2025-08-25 19:21:09 +00:00
Dave Airlie a6e0cbd110 radv: consolidate cooperative matrix array sizes enumeration
Share the code between khr and nv paths to not have to recreate it.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36544>
2025-08-25 18:55:08 +00:00
Dave Airlie a55c036450 radv: add support for coopmat2 flexible dimensions
This allows matricies that are multiples of a base size.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36544>
2025-08-25 18:55:08 +00:00
Dave Airlie 7a96a928a2 nir: add coop mat flexible dimensions lowering.
This adds a generic lowering pass for coop mat flexible dimensions.

This should be suitable for all drivers that implement coop mat2 flexible dimensions
or even just lowering sw exposed sizes to hw sizes.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36544>
2025-08-25 18:55:08 +00:00
Mike Blumenkrantz 39ffc3f629 zink: when sparse unbinding, always wait on main timeline semaphore
this ensures synchronization between gfx/compute work and the sparse queue

fixes KHR-GL46.sparse_buffer_tests.BufferStorageTest_cases_*. on turnip

cc: mesa-stable

Closes: #13747
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36954>
2025-08-25 14:35:25 -04:00
Mike Blumenkrantz 2cf626d17d zink: pass ctx to sparse bind functions
no functional changes

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36954>
2025-08-25 14:35:25 -04:00
Mike Blumenkrantz c9746103f5 zink: break out unflushed batch waiting into separate function/mechanism
this is useful on its own

no functional changes

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36954>
2025-08-25 14:35:25 -04:00
Mike Blumenkrantz 483d53e0e3 zink: ALWAYS_INLINE resource inlines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36954>
2025-08-25 14:35:25 -04:00
Mike Blumenkrantz f9bf524a6d zink: inline zink_resource_access_is_write()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36954>
2025-08-25 14:35:25 -04:00
Connor Abbott bef37336fb vulkan/queue: Fix VkTimelineSemaphoreSubmitInfo sanitization
We're supposed to completely ignore VkTimelineSemaphoreSubmitInfo if
there aren't any timeline semaphores, including the array lengths, which
is made clear by the various VUs already cited by the code. The
vkQueueSubmit() path correctly handled this when asserting but still
dereferenced pWaitSemaphoreValues unconditionally, which could lead to
dereferencing an invalid pointer if waitSemaphoreValueCount is less than
waitSemaphoreCount. The vkQueueSparseBind() path didn't even assert
correctly. Bring vkQueueSparseBind() in line with vkQueueSubmit()
and make both only dereference the wait/signal array once we've
determined it must be present. While we're here, also fix the assert in
vkQueueSubmit() to disallow a waitSemaphoreValueCount of 0 if there are
timeline semaphores present, which conversely is not allowed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36989>
2025-08-25 17:57:47 +00:00
Sagar Ghuge 2cd564c1de anv: Add missing L3 flushes
We are reading out some of the parameters from IR data structure those
have been written previously, on some platforms L3 is not coherent, so
explicitly add those flushes.

Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36952>
2025-08-25 17:36:08 +00:00
Sagar Ghuge 4473e21e2f anv: Enable CS stall for ACCELERATION_STRUCTURE_COPY stage
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36952>
2025-08-25 17:36:08 +00:00
Sagar Ghuge 75d770b4f8 anv: Add missing ACCELERATION_STRUCTURE_READ in barrier handling
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36952>
2025-08-25 17:36:08 +00:00
Jesse Natalie fee83f4fcc d3d12: Move logicop descriptor initialization to after all blits
The blit code is destructive on the framebuffer state, which means
that it can set new render targets. If you have 2 BGRA surfaces bound
for logic ops, then after setting up the surface for the first one,
the blit for the second will end up destroying + re-creating the
surface for the first one.

Let's be robust to this by putting the blit in a first pass, and
then actually initializing all of the descriptors in a second pass.

This is still woefully inefficient but at least it's correct.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36945>
2025-08-25 17:21:37 +00:00
Jesse Natalie cd3885c592 d3d12: Move logicop emulation resource from surface to resource
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36945>
2025-08-25 17:21:37 +00:00
Jesse Natalie 784f93653a d3d12: Support more logic op formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36945>
2025-08-25 17:21:36 +00:00