Mike Blumenkrantz
2e2f4e073d
ci: add venus-lavapipe flake
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36347 >
2025-07-24 12:20:35 +00:00
Valentine Burley
b3cbaf4ee7
zink/ci: Enable more VVL on ANV
...
Enable VVL on ADL, as well as GLES on TGL, and drop some old filters.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36222 >
2025-07-24 11:59:44 +00:00
Jose Maria Casanova Crespo
dac5624ad4
v3d: glMemoryBarriers only flush jobs with tmu_dirty_rcl
...
As we are already updating tmu_dirty_rcl based on the the
shader usage of tmu writes at v3d_emit_gl_shader_state we
can avoid setting it everytime we have a SSBO or image
attached.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36343 >
2025-07-24 11:29:11 +00:00
Samuel Pitoiset
e64b0eda56
radv: remove dead ES emit code on GFX12
...
This is never reached because VS as ES means it's merged into GS as NGG.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36293 >
2025-07-24 11:03:27 +00:00
Samuel Pitoiset
081c7ec7b1
radv: emit PGM_HI_PS in the gfx preamble on GFX12
...
It never changes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36293 >
2025-07-24 11:03:27 +00:00
Hans-Kristian Arntzen
30c2e7871f
anti-lag: Submit timestamps early in a frame.
...
Allows detecting if the queue ends up going idle due to
a cross-queue dependency. Since we're only considering delays from
specific queues, we would not be able to detect low-latency situations
arising from the start of a frame happening on async queues.
Until we observe real work happening for a queue in a frame context,
submit timestamps ahead of any other waits.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34242 >
2025-07-24 09:50:08 +00:00
Hans-Kristian Arntzen
81bb109a3b
anti-lag: Only consider timestamps from queues which have presented.
...
Avoids stray submissions to compute queues to nullify the delay.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34242 >
2025-07-24 09:50:07 +00:00
Daniel Schürmann
722ffe9a73
vulkan: implement VK_AMD_anti_lag as implicit vulkan layer
...
VkLayer_MESA_anti_lag is a lightweight implicit layer which provides
an open-source implementation of the VK_AMD_anti_lag vulkan extension.
The algorithm used by this layer is very simplistic and only aims to
minimize the delay between calls to vkQueueSubmit or vkQueueSubmit2
and the begin of the execution of the submission.
In order to build VkLayer_MESA_anti_lag, pass -Dlayers=anti-lag to meson.
It is possible to either install the layer or to use
VK_ADD_IMPLICIT_LAYER_PATH=<buildpath>/share/vulkan/implicit_layer.d/
for testing purposes.
(Keep in mind that you have to adjust the library_path in the json file in that case.)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34242 >
2025-07-24 09:50:07 +00:00
Daniel Schürmann
699ae0aad9
util/time: add os_time_nanosleep_until() function
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34242 >
2025-07-24 09:50:07 +00:00
Christian Gmeiner
00d905c4b2
etnaviv: Fix negative LOD value encoding in texture descriptors
...
Replace incorrect MIN2 clamping with proper 5.8 signed fixed point
encoding. The hardware expects LOD values in 5.8 format with a range
of -16.0 to +15.99609375. Clamp input values to this valid range
before conversion to handle overflow correctly.
Passes dEQP-GLES3.functional.texture.mipmap.*.max_lod.* on GC7000.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Reviewed-by: Lucas Stach <l.stach@pengutronix.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36303 >
2025-07-24 09:35:06 +00:00
Pavel Ondračka
6fc78f38ae
r300/ci: add one recent flake
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36332 >
2025-07-24 09:21:05 +00:00
Pavel Ondračka
5928eba9eb
r300/ci: check gles2 extensions
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36332 >
2025-07-24 09:21:05 +00:00
Eric Engestrom
f4596e7828
ci/lava: fix heredoc-in-yaml syntax
...
Fixes: 02d07f3380 ("ci/lava: Add SSH job definition")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36239 >
2025-07-24 08:40:44 +00:00
Samuel Pitoiset
0cd745c386
radv: fix a memleak with GS copy shader NIR
...
Really need to refactor this code...
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36317 >
2025-07-24 08:09:00 +00:00
Marek Olšák
8308e394ef
radv: don't sink VS input loads and move them to the top
...
This is likely to be faster.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:17 +00:00
Marek Olšák
4c8a757951
radv,radeonsi: mark VS input loads and poly stipple load speculatable
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:17 +00:00
Marek Olšák
9a9902bc5f
radeonsi: flatten struct si_vs_tcs_input_info
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:17 +00:00
Marek Olšák
355ece3967
radeonsi: get si_shader_info::input::usage_mask from NIR
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:17 +00:00
Marek Olšák
bde0610c0f
radeonsi: recompute FS output IO bases to prevent an LLVM crash
...
Fixes: 7a506d0a41 - glsl: remove gl_nir_opt_dead_builtin_varyings
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:17 +00:00
Marek Olšák
68bcc0ef5d
radeonsi: add a workaround for gfx10.3-11 corruption with R9G9B9E5_FLOAT
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:17 +00:00
Marek Olšák
30acb5a14d
radeonsi: disallow the compute copy for Z/S
...
It doesn't work, and I think this path is actually never exercised.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:17 +00:00
Marek Olšák
4a80272bae
ac/llvm: fix readlane with vectors
...
It crashes in LLVM when the type is not scalar integer.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:17 +00:00
Marek Olšák
543fddb01b
ac/llvm: always use opaque pointers
...
LLVM removed typed pointers a long time ago. These types and bitcasts
had no effect.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:16 +00:00
Marek Olšák
d205772869
ac/llvm: rewrite global & shared loads to share code
...
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:16 +00:00
Marek Olšák
c181db0660
ac/llvm: rewrite global & shared stores to share code
...
The alignment change allows LLVM to select 32-bit stores when 8-bit and
16-bit stores are properly aligned.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:16 +00:00
Marek Olšák
43f18f5615
ac/nir: mark all input loads as reorderable and speculatable (for LICM)
...
These are only memory loads.
We could do the same for LDS loads, which are not truly speculatable
in merged shaders (can't be moved before the barrier), but that's fine
because LICM only moves code out of loops, which can't have barriers.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:16 +00:00
Marek Olšák
a7291074c8
ac/nir: don't vectorize to 96-bit and 128-bit LDS loads (it's slower)
...
LLVM also generates better code with this.
(-0.51% code size in 153 shaders, less SGPR spilling)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:16 +00:00
Marek Olšák
321c8ee8d1
radeonsi/gfx12: enable sparse textures
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:16 +00:00
Marek Olšák
ac52e82868
ac/surface/gfx12: select 64K tiling for sparse MSAA textures
...
addrlib doesn't do it automatically for MSAA
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:16 +00:00
Marek Olšák
8fb8bb6840
ac/surface/gfx12: add addr_from_coord for sparse MSAA textures
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950 >
2025-07-24 06:31:16 +00:00
Mike Blumenkrantz
8a4ef5977e
anv: fix format compatibility check typo
...
the view format is above this
Fixes: 03cdb3078a ("anv: Support multi-planar formats in anv_formats_are_compatible")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36224 >
2025-07-24 00:11:29 +00:00
Mel Henning
658f3db465
nouveau/headers: Update g_nv_name_released.h
...
This pulls in the newest version of the file form
open-gpu-kernel-modules version 575.64.05. This should give us updated
names that correspond to our new hardware support.
The new version also added a ton of lines where the name was "(null)".
Since these would only make our device names more confusing, I've
removed all of these lines in the new version using a script that is
also included in this commit.
Backport-to: 25.2
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36333 >
2025-07-23 20:49:16 +00:00
Faith Ekstrand
36631a4edc
loader: Ignore NOUVEAU_USE_ZINK on Hopper+
...
The old Nouveau GL driver has no support for GPUs after Ada. Instead,
users will always get NVK+Zink on Hopper+. Right now, if the user sets
NOUVEAU_USE_ZINK=false, the loader will return "nouveau" and EGL/GLX
will try to load that, fail, and then fall back to Zink. With this
patch, we instead print a warning message and then load Zink anyway.
Backport-to: 25.2
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36329 >
2025-07-23 20:19:38 +00:00
Alyssa Rosenzweig
8a1a410389
treewide: use SWAP macro
...
Via Coccinelle patch + manual clean up:
@@
identifier temporary, a, b;
type T;
@@
-T temporary = a;
-a = b;
-b = temporary;
+SWAP(a, b);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36297 >
2025-07-23 19:49:47 +00:00
Alyssa Rosenzweig
d51b411f56
dzn: use common SWAP
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36297 >
2025-07-23 19:49:47 +00:00
Job Noorman
986530d231
freedreno: remove ir3_cmdline
...
Nobody is using it anymore.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36313 >
2025-07-23 19:33:35 +00:00
Job Noorman
493a5679e2
ir3/cp: disable cat3 hw bug workaround on a6xx+
...
This hw bug seems to be fixed on a6xx and later.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36324 >
2025-07-23 19:08:30 +00:00
Antonio Ospite
5f843f6dd6
zink: fix assigning _Bool to _Bool*
...
When building for C23 the compiler warns about assigning boolean to
a different type.
Change the code fixing the following error:
-----------------------------------------------------------------------
../src/gallium/drivers/zink/zink_query.c: In function ‘find_or_allocate_qp’:
../src/gallium/drivers/zink/zink_query.c:213:25: error: incompatible types when assigning to type ‘_Bool *’ from type ‘_Bool’
213 | vkq_needs_reset = false;
| ^~~~~
-----------------------------------------------------------------------
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Fixes: 92811d9a56 ("zink: use maint9 implicit query resets when available")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36326 >
2025-07-23 18:51:23 +00:00
Aaron Ruby
525513fd23
gfxstream: Modify deviceName, driverVersion, driverName, driverInfo ...
...
... to report that Vulkan is running through a gfxstream driver to the
host driver. This matches what Venus does.
TODOs added for driverID, need spec'd driverID for gfxstream in Mesa.
Example:
Device Properties and Extensions:
=================================
GPU0:
VkPhysicalDeviceProperties:
---------------------------
apiVersion = 1.3.0 (4206592)
driverVersion = 525.147.5.0 (2204418368)
vendorID = 0x10de
deviceID = 0x1fb9
deviceType = PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
deviceName = Virtio-GPU GFXStream (Quadro T1000)
pipelineCacheUUID = 5e84b6ed-4e70-35e3-a855-d75f23b64fd5
VkPhysicalDeviceDriverProperties:
---------------------------------
driverID = DRIVER_ID_NVIDIA_PROPRIETARY
driverName = gfxstream
driverInfo = Mesa 25.1.0
conformanceVersion:
major = 1
minor = 3
subminor = 3
patch = 1
Reviewed-by: Gurchetan Singh <gurchetansingh@google.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36290 >
2025-07-23 17:26:25 +00:00
Faith Ekstrand
22c624d75b
vulkan/meta: Supply image view usage in vk_meta_clear_*_image()
...
This was the only meta function (including those built into honeykrisp)
which wasn't setting view usage so we can also assert that it's always
provided.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36301 >
2025-07-23 17:00:02 +00:00
Faith Ekstrand
f4b01bbfe7
nvk: Add an nvk_is_conformant() helper
...
The checks are getting more complicated so it's better to have a helper
than a simple boolean with a complex expression.
Backport-to: 25.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36319 >
2025-07-23 16:44:11 +00:00
Faith Ekstrand
d3ab663a77
nvk: Bump the conformance version to 1.4.3
...
Backport-to: 25.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36319 >
2025-07-23 16:44:11 +00:00
Samuel Pitoiset
c05ef04152
radv/ci: fix list of expected failures for VEGA10/NAVI10
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36315 >
2025-07-23 16:29:20 +00:00
Eric Engestrom
c2c8bced59
docs: update calendar for 25.2.0-rc2
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36318 >
2025-07-23 16:23:47 +00:00
Caio Oliveira
8783828f3d
intel/genxml: Remove support for start/end atttributes
...
Keep the support in gen_sort_xml.py to allow it still convert
old MRs into the new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138 >
2025-07-23 16:02:14 +00:00
Caio Oliveira
c418cb85f7
intel/genxml: Convert field format from start/end to dword/bits
...
And change the gen_sort_xml.py script to default to the new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138 >
2025-07-23 16:02:14 +00:00
Caio Oliveira
fb8f14820a
intel/genxml: Add support for dword/bits in fields to rest of the code
...
Change code to temporarily support both the start/end old format and the
dword/bits new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138 >
2025-07-23 16:02:14 +00:00
Caio Oliveira
001f207ee0
intel/genxml: Add support for dword/bits in fields to gen_sort_tags.py script
...
Add a `--bits-format` argument to normalize the output to either of the
formats described below. For now, defaults to the old format.
The documentation in PRMs and BSpec describe the fields with the dword
and the bit range. Using the same convention makes easier to spot
issues.
Old format:
```
<field name="Disable SLM Read Merge Optimization" start="38" end="38" type="bool" />
<field name="Pixel Async Compute Thread Limit" start="39" end="41" type="uint" prefix="PACTL">
```
New format:
```
<field name="Disable SLM Read Merge Optimization" dword="1" bits="6:6" type="bool" />
<field name="Pixel Async Compute Thread Limit" dword="1" bits="9:7" type="uint" prefix="PACTL">
```
For Groups, we store the dword and if needed a offset_bits, in case
a group starts in a non-aligned position. Size and count for groups are
not changed.
Do this first for gen_sort_tags.py in case is convenient to have for the
stable tree to convert future patches from the new back into the old
format. Later patches will add support to the rest of the code.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138 >
2025-07-23 16:02:13 +00:00
Caio Oliveira
395672b013
intel/decoder/tests: Sort gentest.xml file
...
Avoid noise when changing to the new GenXML field format -- which would
try to also sort it. Also add this file to be checked as part of tests.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138 >
2025-07-23 16:02:13 +00:00
Eric Engestrom
69bede258d
lavapipe/ci: document recent flakes
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36307 >
2025-07-23 15:30:53 +00:00