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radv: remove dead ES emit code on GFX12

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This is never reached because VS as ES means it's merged into GS as NGG.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36293>
This commit is contained in:
Samuel Pitoiset
2025-07-22 11:45:38 +02:00
committed by Marge Bot
parent 081c7ec7b1
commit e64b0eda56
1 changed files with 9 additions and 14 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+9 -14
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@@ -2109,20 +2109,15 @@ radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *sh
const struct radv_physical_device *pdev = radv_device_physical(device);
const uint64_t va = radv_shader_get_va(shader);
if (pdev->info.gfx_level >= GFX12) {
gfx12_push_sh_reg(cmd_buffer, shader->info.regs.pgm_lo, va >> 8);
gfx12_push_sh_reg(cmd_buffer, shader->info.regs.pgm_lo + 4, S_00B324_MEM_BASE(va >> 40));
gfx12_push_sh_reg(cmd_buffer, shader->info.regs.pgm_rsrc1, shader->config.rsrc1);
gfx12_push_sh_reg(cmd_buffer, shader->info.regs.pgm_rsrc2, shader->config.rsrc2);
} else {
radeon_begin(cmd_buffer->cs);
radeon_set_sh_reg_seq(shader->info.regs.pgm_lo, 4);
radeon_emit(va >> 8);
radeon_emit(S_00B324_MEM_BASE(va >> 40));
radeon_emit(shader->config.rsrc1);
radeon_emit(shader->config.rsrc2);
radeon_end();
}
assert(pdev->info.gfx_level < GFX11);
radeon_begin(cmd_buffer->cs);
radeon_set_sh_reg_seq(shader->info.regs.pgm_lo, 4);
radeon_emit(va >> 8);
radeon_emit(S_00B324_MEM_BASE(va >> 40));
radeon_emit(shader->config.rsrc1);
radeon_emit(shader->config.rsrc2);
radeon_end();
}
static void