1406eafbcd
nir/lower_explicit_io: add alignment parameters to address builder
...
We will need this when building shifted addresses. Since adding these
parameters has a lot of code churn which would distract from the main
changes, it is split-off in a separate commit.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
553a439b54
nir/lower_explicit_io: use nir_io_offset to pass around addresses
...
We will add support for shifted addresses; this commit makes sure the
APIs of the functions already support passing shifts.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
4c9afbd01d
nir/lower_explicit_io: add helper to build address
...
The helper is used to build the address passed to
build_explicit_io_load/store. For now, it simply takes care of adding
the component offset when scalarizing. In the future, this can be used
to do more complex address manipulations, like calculating the full
deref chain address.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
1fffba12a0
nir/lower_explicit_io: make offset calculation reusable
...
nir_explicit_io_address_from_deref implicitly builds the offset but only
makes the full address available. Split-out the offset calculation in a
separate function so we can reuse it elsewhere.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
b0bc97cb43
nir/opt_load_store_vectorize: fix wrap check for scaled offsets
...
Hardware will typically do bounds checking on the final scaled address
so the wrap check should do the same.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
cb773dec8c
nir/opt_load_store_vectorize: add support for offset_shift
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
249e27c9c7
nir/opt_load_store_vectorize: allow per-instruction offset scaling
...
We currently support offset scaling on a per-intrinsic type basis. Since
the introduction of the offset_shift index, different instantiations of
the same type can now have a different scale. Add support for this by
calculating the offset scale on the fly for instructions that have
offset_shift.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
7fe484e373
nir/lower_mem_access_bit_sizes: add partial support for offset_shift
...
Note: this was implemented and tested for ir3. The code paths that are
never used there [1] seem non-trivial to implement. Since they cannot be
easily tested, asserts and TODOs are added to ensure we don't
accidentally hit them for intrinsics with offset_shift.
[1]: these paths are never used on ir3 since lower_mem_access_bit_sizes
is only used for SSBO accesses to lower 64b accesses (which are 64b
aligned) to 32b ones. So we'll never request an increase of alignment.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
cd72d8e366
nir/opt_shrink_vectors: add support for offset_shift
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
f876adc372
nir/lower_wrmasks: add support for offset_shift
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
b85c379945
nir/lower_wrmasks: don't adjust BASE
...
The immediate addition can easily be handled by nir_opt_offsets, which
will also take any driver limits into account.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
dd296a6d80
nir/lower_io_to_scalar: add support for offset_shift
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
59eb95cd2f
nir/lower_atomics: add support for offset_shift
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
513412c893
nir,ir3: add offset_shift index to SSBO access intrinsics
...
In ir3, SSBO offsets are in units of the accessed type size so we want
to start using the new offset_shift index.
Even though the shift is implicit for the ir3 intrinsics, we use
nir_intrinsic_copy_const_indices when creating them so we need to make
sure our indices match the ones used by the generic intrinsics.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
355c9b88f7
nir: add some helpers for dealing with offset_shift
...
For intrinsics supporting offset_shift, dealing with their offset is a
bit tricky as we cannot simply add a byte offset to it anymore (which is
what most passes want to do). This commit adds some helpers to add byte
offsets (and adjusting offset_shift accordingly) so that individual
passes don't have to worry about this.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
7cc09e9952
nir: add offset_shift intrinsic index
...
For load/store intrinsics that take an offset, this specifies the amount
the offset is shifted left to calculate the final offset:
offset = (offset_src + base) << offset_shift
This is useful for backends that have memory operations that use offset
units other than bytes (i.e., where the shift is implicit).
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
ebea9ce825
nir: add nir_src_is_deref helper
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:30 +00:00
65d559fcf6
tu: pass SSBO/UBO min alignment to SPIR-V frontend
...
Values are taken from minStorageBufferOffsetAlignment and
minUniformBufferOffsetAlignment.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092 >
2025-08-20 07:51:29 +00:00
e10d955bc4
radv/ci: document a very recent ACO regression on GFX12
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36806 >
2025-08-20 06:31:15 +00:00
eaaef8db5a
radv/ci: make radv-gfx1201-vkcts a pre-merge job
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36806 >
2025-08-20 06:31:14 +00:00
640aed5727
radv/ci: reduce the timeout for radv-gfx1201-vkcts
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36806 >
2025-08-20 06:31:14 +00:00
9b9f62125b
radv/ci: use 3 parallel jobs for radv-gfx1201-vkcts
...
For pre-merge testing, it's required to be around 10 minutes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36806 >
2025-08-20 06:31:14 +00:00
d25952c3d3
radv/ci: update expected list of failures/flakes on GFX1201
...
50 runs in a row without any unexpected failures/hangs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36806 >
2025-08-20 06:31:14 +00:00
2a8c5ebc77
ir3: enable scalar predicates
...
Enable the use of scalar predicates by marking predicate dsts as uniform
when possible during instruction emission and in opt_predicates.
Totals:
Instrs: 48207402 -> 47967272 (-0.50%); split: -0.54%, +0.05%
CodeSize: 101907026 -> 101768626 (-0.14%); split: -0.15%, +0.01%
NOPs: 8386320 -> 8165410 (-2.63%); split: -2.88%, +0.25%
MOVs: 1468853 -> 1470546 (+0.12%); split: -0.17%, +0.28%
COVs: 823724 -> 823746 (+0.00%); split: -0.01%, +0.01%
Full: 1716708 -> 1716767 (+0.00%); split: -0.00%, +0.01%
(ss): 1113167 -> 1168194 (+4.94%); split: -0.15%, +5.09%
(sy): 552317 -> 552288 (-0.01%); split: -0.10%, +0.09%
(ss)-stall: 4013046 -> 4261336 (+6.19%); split: -0.11%, +6.30%
(sy)-stall: 16741190 -> 16748983 (+0.05%); split: -0.17%, +0.22%
STPs: 18895 -> 18901 (+0.03%); split: -0.02%, +0.05%
LDPs: 23853 -> 23762 (-0.38%); split: -0.39%, +0.01%
Preamble Instrs: 11506988 -> 11493425 (-0.12%); split: -0.12%, +0.01%
Early Preamble: 121339 -> 121695 (+0.29%)
Last helper: 11686328 -> 11628618 (-0.49%); split: -0.72%, +0.23%
Cat0: 9241457 -> 9020508 (-2.39%); split: -2.62%, +0.22%
Cat1: 2353411 -> 2354860 (+0.06%); split: -0.17%, +0.23%
Cat2: 17468471 -> 17447932 (-0.12%); split: -0.12%, +0.00%
Cat6: 515728 -> 515643 (-0.02%); split: -0.02%, +0.00%
Cat7: 1637795 -> 1637789 (-0.00%); split: -0.05%, +0.05%
Totals from 33275 (20.20% of 164705) affected shaders:
Instrs: 30329487 -> 30089357 (-0.79%); split: -0.86%, +0.07%
CodeSize: 59715922 -> 59577522 (-0.23%); split: -0.26%, +0.03%
NOPs: 6265422 -> 6044512 (-3.53%); split: -3.86%, +0.33%
MOVs: 1058197 -> 1059890 (+0.16%); split: -0.23%, +0.39%
COVs: 427513 -> 427535 (+0.01%); split: -0.02%, +0.03%
Full: 548495 -> 548554 (+0.01%); split: -0.01%, +0.02%
(ss): 769340 -> 824367 (+7.15%); split: -0.21%, +7.36%
(sy): 368276 -> 368247 (-0.01%); split: -0.14%, +0.13%
(ss)-stall: 3076333 -> 3324623 (+8.07%); split: -0.15%, +8.22%
(sy)-stall: 10740547 -> 10748340 (+0.07%); split: -0.27%, +0.34%
STPs: 12872 -> 12878 (+0.05%); split: -0.02%, +0.07%
LDPs: 20808 -> 20717 (-0.44%); split: -0.45%, +0.01%
Preamble Instrs: 6354490 -> 6340927 (-0.21%); split: -0.22%, +0.01%
Early Preamble: 15233 -> 15589 (+2.34%)
Last helper: 8106631 -> 8048921 (-0.71%); split: -1.04%, +0.32%
Cat0: 6888653 -> 6667704 (-3.21%); split: -3.51%, +0.30%
Cat1: 1541452 -> 1542901 (+0.09%); split: -0.25%, +0.35%
Cat2: 10963398 -> 10942859 (-0.19%); split: -0.19%, +0.00%
Cat6: 265945 -> 265860 (-0.03%); split: -0.03%, +0.00%
Cat7: 1164800 -> 1164794 (-0.00%); split: -0.07%, +0.07%
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36614 >
2025-08-20 06:14:02 +00:00
cccb3ecc6a
ir3/opt_predicates: move some helpers up
...
We'll need them earlier in the next commit.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36614 >
2025-08-20 06:14:02 +00:00
0223ab01b7
ir3/isa: add encoding for scalar predicates
...
Predicate registers can be written from the scalar ALU by using a
special cat2 encoding: if the dst is encoded as a0.c, the instruction
will execute on the scalar ALU and write to p0.c.
This commit follows the blob and disassembles scalar predicates as
up0.c. The "u" presumably stands for "uniform".
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36614 >
2025-08-20 06:14:02 +00:00
25ab37ae5b
ir3: make backend aware of scalar predicates
...
Predicate registers can be written from the scalar ALU by using a
special cat2 encoding: if the dst is encoded as a0.c, the instruction
will execute on the scalar ALU and write to p0.c.
This commit makes the ir3 backend aware of scalar predicates. A new
register flag (IR3_REG_UNIFORM) is added that can be used to mark
predicate dsts as being written by the scalar ALU. For such dsts, the
same synchronization rules apply as for shared registers written by the
scalar ALU (e.g., (ss) is needed to read them from the vector ALU).
Scalar predicates can be used in the early preamble, which makes control
flow available there.
In many ways, the backend treats IR3_REG_UNIFORM the same as
IR3_REG_SHARED. A new flag was added because IR3_REG_SHARED is mainly
used to denote a separate register file, not as a flag to indicate usage
by the scalar ALU. Scalar predicates still use the normal predicate
register file but allow it to be written from the scalar ALU.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36614 >
2025-08-20 06:14:02 +00:00
bd28a40bd4
ir3/legalize: don't special-case early-preamble a1 reads
...
We can just generically read from the regmask.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36614 >
2025-08-20 06:14:02 +00:00
8760c36579
ir3: use shared srcs for demote/kill condition
...
No reason to force vector srcs.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36614 >
2025-08-20 06:14:02 +00:00
dbfed965ae
ir3: use ir3_get_predicate for demote/kill
...
Instead of duplicating its functionality.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36614 >
2025-08-20 06:14:02 +00:00
2158211eeb
ir3: allow shared srcs for ldc.k
...
This works just fine and opens up a lot more opportunities for early
preamble. Note that I haven't seen actual cases where the index is large
enough to need a register but verified in computerator that it works.
Totals:
MaxWaves: 2377648 -> 2377666 (+0.00%)
Instrs: 48207402 -> 48219491 (+0.03%); split: -0.01%, +0.03%
CodeSize: 101907026 -> 101929790 (+0.02%); split: -0.01%, +0.03%
NOPs: 8386320 -> 8392647 (+0.08%); split: -0.03%, +0.10%
MOVs: 1468853 -> 1474439 (+0.38%); split: -0.19%, +0.57%
Full: 1716708 -> 1716655 (-0.00%)
(ss): 1113167 -> 1115183 (+0.18%); split: -0.05%, +0.23%
(sy): 552317 -> 552334 (+0.00%); split: -0.10%, +0.10%
(ss)-stall: 4013046 -> 4011814 (-0.03%); split: -0.10%, +0.06%
(sy)-stall: 16741190 -> 16738674 (-0.02%); split: -0.20%, +0.19%
Preamble Instrs: 11506988 -> 11422360 (-0.74%); split: -0.79%, +0.06%
Early Preamble: 121339 -> 123955 (+2.16%)
Last helper: 11686328 -> 11688700 (+0.02%); split: -0.01%, +0.03%
Cat0: 9241457 -> 9248390 (+0.08%); split: -0.02%, +0.10%
Cat1: 2353411 -> 2359061 (+0.24%); split: -0.12%, +0.36%
Cat7: 1637795 -> 1637301 (-0.03%); split: -0.18%, +0.14%
Totals from 5370 (3.26% of 164705) affected shaders:
MaxWaves: 66838 -> 66856 (+0.03%)
Instrs: 4127945jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36673 >
2025-08-20 05:10:23 +00:00
ef09df004e
compiler/types: handle BFLOAT16 when decoding blob
...
New type was not handled in the switch which lead to hitting following
assert when running tests with pipeline cache:
deqp-vk: ../src/compiler/glsl_types.c:3334: decode_type_from_blob: Assertion `!"Cannot decode type!"' failed.
Fixes: 9e5d7eb88dtapani.palli@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36833 >
2025-08-20 04:12:00 +00:00
9452f2ca3f
amd/vpelib: Minor Refactor
...
[WHY]
There will be more conditions for bypassing degamma, so refactor.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com >
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36809 >
2025-08-20 10:42:01 +08:00
dda6a76b54
amd/vpelib: check stream_count as well before accessing streams
...
[WHY]
It was found that the caller may call with stream_count = 0, while
streams array is some garbage.
it randomly ends up output_ctx being modified and leading to validation
failure.
[HOW]
Add checking to the stream_count.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com >
Signed-off-by: Roy Chan <Roy.Chan@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36809 >
2025-08-20 10:42:01 +08:00
2b50600a71
amd/vpelib: Extend TMZ value to 8 bit
...
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com >
Signed-off-by: Jiali Zhao <Jiali.Zhao@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36809 >
2025-08-20 10:42:01 +08:00
c26cf7f74d
amd/vpelib: VPE Events
...
[WHY]
For further debugging need to know about the build cmd variables.
[HOW]
Added these input and output paramaters to vpe events.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com >
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36809 >
2025-08-20 10:42:01 +08:00
a486404e4d
amd/vpelib: General cleanup / optimization tasks
...
Various small optimizations that have been accumulating, deal with them
in one commit:
- Add erase functionality for vector util, remove memsets for time opt.
- Update should_gen_cmd_info to take in any stream variables.
- Program funcs should directly program - update mpcc mux hook func to
take in blend_mode.
- Add reserved bits for debug flags.
Signed-off-by: Brendan Steven, Leder <BrendanSteven.Leder@amd.com >
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36809 >
2025-08-20 10:42:01 +08:00
e5cdc78e0e
amd/vpelib: Move predication size calculation to bufs_req
...
Calculation for the worst case scenario in bufs_req should also include
predication command size.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com >
Signed-off-by: Andrzei Okenczyc <Andrzej.Okenczyc@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36809 >
2025-08-20 10:42:01 +08:00
fbeaca1202
amd/vpelib: Add necessary pointer casting
...
Add necessary pointer casting to prevent unexpected behavior
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com >
Signed-off-by: Navid Assadian <Navid.Assadian@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36809 >
2025-08-20 10:42:01 +08:00
bdda1cf5ef
va: Use { 0 } initialize struct
...
../src/gallium/frontends/va/config.c(574): error C2059: syntax error: '}'
MSVC 2019 doesn't support for it yet
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: David Rosca <david.rosca@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36843 >
2025-08-20 02:02:55 +00:00
76c1243dc8
va: Remove unused variable pscreen
...
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: David Rosca <david.rosca@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36843 >
2025-08-20 02:02:54 +00:00
4fda724fd4
brw: Avoid invalid access when compacting out-of-bounds JIP/UIP
...
Usually JIP will be valid, but as part of other changes, it will be
possible to have a shader that have multiple EOT messages and end with
and ENDIF instruction. Its JIP will point after the program ends.
This is fine but was tripping up the compaction code.
Change compaction to not read its internal structures beyond the last
instruction.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36822 >
2025-08-20 00:54:41 +00:00
a5433b44e6
nvk/ci: document some flakes
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36857 >
2025-08-20 00:41:19 +00:00
439a0a5c2e
turnip/ci: document a flake
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36857 >
2025-08-20 00:41:19 +00:00
65b0f2ebe0
etnaviv/ci: document some flakes
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36857 >
2025-08-20 00:41:19 +00:00
a5b516804e
r300/ci: document flake
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36857 >
2025-08-20 00:41:19 +00:00
9cb27063fd
zink+turnip/ci: document fixed tests
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36857 >
2025-08-20 00:41:19 +00:00
19021733e6
zink+turnip/ci: document regression in b22806705c...cac3b4f404
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36857 >
2025-08-20 00:41:19 +00:00
03b7054c30
pan/midgard: avoid implicit cast-warning on Clang
...
BITFIELD_MASK() returns a 32-bit unsigned integer, and Clang complains
if we assign it to a 16-bit unsigned integer without a cast. Let's add
that cast.
While we're at it, add an assert() to make it clear to the compiler that
the condition in BITFIELD_MASK() can be optimized away.
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org >
Tested-by: Yiwei Zhang <zzyiwei@chromium.org >
Reviewed-by: Eric R. Smith <eric.smith@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36606 >
2025-08-20 00:05:36 +00:00
e5fda871fd
panvk: avoid implicit cast-warning on Clang
...
BITFIELD_MASK() returns a 32-bit unsigned integer, and Clang complains
if we assign it to a 16-bit unsigned integer without a cast. Let's add
that cast.
While we're at it, add an assert() to make it clear to the compiler that
the condition in BITFIELD_MASK() can be optimized away.
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org >
Tested-by: Yiwei Zhang <zzyiwei@chromium.org >
Reviewed-by: Eric R. Smith <eric.smith@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36606 >
2025-08-20 00:05:36 +00:00
Job Noorman