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Author SHA1 Message Date
Samuel Pitoiset 053c19e996 zink/ci: update expected list of failures for VANGOGH 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31385>
 2024-10-01 08:33:51 +00:00
Samuel Pitoiset 493d5910a3 radv: advertise sampler2DViewOf3D 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31385>
 2024-10-01 08:33:51 +00:00
Samuel Pitoiset f5805bcb8e radv: implement 2D views of 3D images using 2D_ARRAY descriptors on GFX9+ 
This also allows us to disable a workaround in ACO for GFX9, but it
can't be removed completely because RadeonSI needs to use it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31385>
 2024-10-01 08:33:51 +00:00
Samuel Pitoiset dc5ef90547 ac/surface: add RADEON_SURF_VIEW_3D_AS_2D_ARRAY for GFX9+ 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31385>
 2024-10-01 08:33:51 +00:00
Vignesh Raman 04f30870b6 ci: add Gen10 Arm Mali firmware to rootfs 
Add firmware for Gen10 Arm Mali GPUs directly to rootfs since
it is not available from debian package. For the panthor kernel
driver to be able to execute jobs on the GPU it needs this firmware.

Update the kernel, which contains a fix to build the panthor driver
as module and use HWCI_KERNEL_MODULES to load panthor module.

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31342>
 2024-10-01 07:57:42 +00:00
Mike Blumenkrantz 8494849b92 vl: add pipe_video_buffer::flags to sync up with pipe_resource::flags 
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31319>
 2024-10-01 17:00:39 +10:00
Dave Airlie caafa50af6 va: add some h264 fields 
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31319>
 2024-10-01 17:00:36 +10:00
Valentine Burley 1e623ad308 freedreno/ci: Document new flake 
KHR-GL46.texture_view.view_classes started flaking after the CTS
uprev and is blocking merges.

Fixes: 3178170516 ("ci: bump gl cts versions")

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31456>
 2024-10-01 06:17:13 +00:00
Marek Olšák 765d1c4757 st/mesa: copy some TES shader info fields to TCS 
radeonsi would like to have the tess prim mode and spacing in TCS.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31448>
 2024-10-01 02:48:30 +00:00
Hyunjun Ko f76781feb8 anv: enable KHR_video_maintenance1 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
 2024-10-01 10:45:14 +09:00
Hyunjun Ko ac2fd8ae66 anv: support VK_IMAGE_CREATE_VIDEO_PROFILE_INDEPENDENT_BIT_KHR 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
 2024-10-01 10:45:14 +09:00
Hyunjun Ko 0981d20850 anv: support for inline query for vulkan video 
v1. Removed the unnecessary query begin code.
(lionel.g.landwerlin@intel.com)

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
 2024-10-01 10:45:14 +09:00
Hyunjun Ko 1b06d4a8ea anv: consider VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR when 
allocating mv storgae.

Fixes: 3ec8f7f99 ("anv/video: initial support for h264 encoding")

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
 2024-10-01 10:45:14 +09:00
Hyunjun Ko 8a3f852119 anv/video: support VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DISABLED_BIT_KHR. 
Which means to support CQP mode.

Fixes: 3ec8f7f99 ("anv/video: initial support for h264 encoding")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
 2024-10-01 10:45:14 +09:00
Faith Ekstrand bf013cf8de vulkan: Add a comment explainint SEVERITY_WARNING_BIT for vk_error*() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31449>
 2024-10-01 00:48:36 +00:00
Gert Wollny 29fd096d91 Revert: r600/sfn: call nir_lower_doubles explicitely" 
This reverts commit 36c81b5e88.

With

   nir/opt_algebraic: Allow two-step lowering of ftrunc@64 to use ffract@64

it is no longer necessary to call nir_lower_doubles explicitely in r600/sfn.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29281>
 2024-09-30 23:51:02 +00:00
Gert Wollny f19f1ec17b nir/opt_algebraic: Allow two-step lowering of ftrunc@64 to use ffract@64 
If ftrunc@64 is lowered by nir_lower_doubles it is turned into a
comparable long series of 32 bit operations. If the hardware
supports ffract@64 then nir_opt_algebraic can first lower ftrunc@64
to use some combinations with ffloor@64. They can then be turned
into a combination of fsub@64 and ffract@64 resulting in less
all-over instructions.

Fixes: 5218cff34b
   nir/algebraic: avoid double lowering of some fp64 operations

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29281>
 2024-09-30 23:51:02 +00:00
Konstantin Seurer 8aa314d3e1 lavapipe: Set minAccelerationStructureScratchOffsetAlignment to 8 
The 128 alignment was copied from RADV (which does not need it). 8 bytes
should be enough.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31365>
 2024-09-30 23:24:05 +00:00
Konstantin Seurer 4cb8ecd47c Revert "lavapipe: Do not return in report_ray_intersection" 
This reverts commit 466bbaf40f.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31405>
 2024-09-30 22:58:12 +00:00
Jules Blok 1c119b1d95 docs: Update status of VK_EXT_depth_clamp_control support 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31411>
 2024-09-30 22:18:27 +00:00
Jules Blok 6e39d56252 nvk: Add support for VK_EXT_depth_clamp_control 
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31411>
 2024-09-30 22:18:27 +00:00
Jules Blok 4994c5a243 anv: Add support for VK_EXT_depth_clamp_control 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31411>
 2024-09-30 22:18:27 +00:00
Jules Blok 12b4ab3b04 radv: Add support for VK_EXT_depth_clamp_control 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31411>
 2024-09-30 22:18:27 +00:00
Jules Blok b9af5564bb vulkan: Add support for VK_EXT_depth_clamp_control 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31411>
 2024-09-30 22:18:27 +00:00
Paulo Zanoni bd33917509 anv: remove another copy of the texture cache pipe_control workaround 
The workaround is already implemented by
batch_emit_pipe_control_write(), we don't need to do it here as well.

This was spotted by Lionel Landwerlin. The credits go to him, I just
wrote the patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31412>
 2024-09-30 21:44:12 +00:00
Paulo Zanoni fd4a44430c anv: remove duplicate pipe_control workaround 
Commit a603cc0633 ("anv: move some pc was to
batch_emit_pipe_control_write") moved some WAs from
emit_apply_pipe_flushes() to batch_emit_pipe_control_write(), but it
turns out one of them was already there since cf7e1f3817 ("anv,
iris: add missing CS_STALL bit for GPGPU texture invalidation").

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31412>
 2024-09-30 21:44:12 +00:00
Patrick Lerda 242da61b9d r600/sfn: fix class Shader object last_alu_with_indirect_reg memory leak 
For instance, this issue is triggered with "piglit/bin/glsl-vs-arrays -auto -fbo":
Direct leak of 104 byte(s) in 1 object(s) allocated from:
    #0 0x7f2fab415f57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57)
    #1 0x7f2f9fd9d541 in __gnu_cxx::new_allocator<std::__detail::_Hash_node_base*>::allocate(unsigned long, void const*) /usr/include/c++/11.4.0/ext/new_allocator.h:127
    #2 0x7f2f9fd9d541 in std::allocator_traits<std::allocator<std::__detail::_Hash_node_base*> >::allocate(std::allocator<std::__detail::_Hash_node_base*>&, unsigned long) /usr/include/c++/11.4.0/bits/alloc_traits.h:464
    #3 0x7f2f9fd9d541 in std::__detail::_Hashtable_alloc<std::allocator<std::__detail::_Hash_node<std::pair<int const, r600::Instr*>, false> > >::_M_allocate_buckets(unsigned long) /usr/include/c++/11.4.0/bits/hashtable_policy.h:1927
    #4 0x7f2f9fd9d541 in std::_Hashtable<int, std::pair<int const, r600::Instr*>, std::allocator<std::pair<int const, r600::Instr*> >, std::__detail::_Select1st, std::equal_to<int>, std::hash<int>, std::__detail::_Mod_range_hashing, std::__detail::_Default_ranged_hash, std::__detail::_Prime_rehash_policy, std::__detail::_Hashtable_traits<false, false, true> >::_M_allocate_buckets(unsigned long) /usr/include/c++/11.4.0/bits/hashtable.h:440
    #5 0x7f2f9fd9d541 in std::_Hashtable<int, std::pair<int const, r600::Instr*>, std::allocator<std::pair<int const, r600::Instr*> >, std::__detail::_Select1st, std::equal_to<int>, std::hash<int>, std::__detail::_Mod_range_hashing, std::__detail::_Default_ranged_hash, std::__detail::_Prime_rehash_policy, std::__detail::_Hashtable_traits<false, false, true> >::_M_rehash_aux(unsigned long, std::integral_constant<bool, true>) /usr/include/c++/11.4.0/bits/hashtable.h:2382
    #6 0x7f2f9fd9d541 in std::_Hashtable<int, std::pair<int const, r600::Instr*>, std::allocator<std::pair<int const, r600::Instr*> >, std::__detail::_Select1st, std::equal_to<int>, std::hash<int>, std::__detail::_Mod_range_hashing, std::__detail::_Default_ranged_hash, std::__detail::_Prime_rehash_policy, std::__detail::_Hashtable_traits<false, false, true> >::_M_rehash(unsigned long, unsigned long const&) /usr/include/c++/11.4.0/bits/hashtable.h:2361
    #7 0x7f2f9fd9d541 in std::_Hashtable<int, std::pair<int const, r600::Instr*>, std::allocator<std::pair<int const, r600::Instr*> >, std::__detail::_Select1st, std::equal_to<int>, std::hash<int>, std::__detail::_Mod_range_hashing, std::__detail::_Default_ranged_hash, std::__detail::_Prime_rehash_policy, std::__detail::_Hashtable_traits<false, false, true> >::_M_insert_unique_node(unsigned long, unsigned long, std::__detail::_Hash_node<std::pair<int const, r600::Instr*>, false>*, unsigned long) /usr/include/c++/11.4.0/bits/hashtable.h:2021
    #8 0x7f2f9fd9e7f8 in std::__detail::_Map_base<int, std::pair<int const, r600::Instr*>, std::allocator<std::pair<int const, r600::Instr*> >, std::__detail::_Select1st, std::equal_to<int>, std::hash<int>, std::__detail::_Mod_range_hashing, std::__detail::_Default_ranged_hash, std::__detail::_Prime_rehash_policy, std::__detail::_Hashtable_traits<false, false, true>, true>::operator[](int&&) /usr/include/c++/11.4.0/bits/hashtable_policy.h:741
    #9 0x7f2f9fd9f6fe in std::unordered_map<int, r600::Instr*, std::hash<int>, std::equal_to<int>, std::allocator<std::pair<int const, r600::Instr*> > >::operator[](int&&) /usr/include/c++/11.4.0/bits/unordered_map.h:984
    #10 0x7f2f9fd9f6fe in r600::Shader::InstructionChain::visit(r600::AluInstr*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:1358
    #11 0x7f2f9fd8f309 in r600::Shader::emit_instruction(r600::Instr*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:1419
    #12 0x7f2f9fd8f822 in r600::RegisterReadHandler::visit(r600::LocalArray&) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:1040
    #13 0x7f2f9fd8e726 in r600::Shader::emit_load_reg_indirect(nir_intrinsic_instr*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:993
    #14 0x7f2f9fd8de5c in r600::Shader::process_instr(nir_instr*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:848
    #15 0x7f2f9fd8de5c in r600::Shader::process_block(nir_block*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:836
    #16 0x7f2f9fd962f2 in r600::Shader::process_cf_node(nir_cf_node*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:669
    #17 0x7f2f9fdac01a in r600::Shader::process(nir_shader*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:537
    #18 0x7f2f9fdac3d1 in r600::Shader::translate_from_nir(nir_shader*, pipe_stream_output_info const*, r600_shader*, r600_shader_key const&, r600_chip_class, radeon_family) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:494
    #19 0x7f2f9fb5c8f5 in r600_shader_from_nir ../src/gallium/drivers/r600/r600_sfn.cpp:111
    #20 0x7f2f9fb5e50c in r600_pipe_shader_create ../src/gallium/drivers/r600/r600_shader.c:198
    #21 0x7f2f9fb96642 in r600_shader_select ../src/gallium/drivers/r600/r600_state_common.c:961
    #22 0x7f2f9fb97340 in r600_create_shader_state ../src/gallium/drivers/r600/r600_state_common.c:1056
    #23 0x7f2f9e060f82 in st_create_common_variant ../src/mesa/state_tracker/st_program.c:720
    #24 0x7f2f9e06e779 in st_get_common_variant ../src/mesa/state_tracker/st_program.c:773
    #25 0x7f2f9e06f78d in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:1259
    #26 0x7f2f9e06f78d in st_finalize_program ../src/mesa/state_tracker/st_program.c:1345
    #27 0x7f2f9ead0f20 in st_link_glsl_to_nir ../src/mesa/state_tracker/st_glsl_to_nir.cpp:723
    #28 0x7f2f9ead0f20 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_nir.cpp:951
    #29 0x7f2f9e9b0d15 in link_program ../src/mesa/main/shaderapi.c:1336
    #30 0x7f2f9e9b0d15 in link_program_error ../src/mesa/main/shaderapi.c:1447

Fixes: ddb167e81a ("r600/sfn: Handle indirect array load/store dependencies better")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27334>
 2024-09-30 21:16:56 +00:00
Patrick Lerda b660c73693 r600/sfn: fix class Shader object m_register_allocations memory leak 
For instance, this issue is triggered with "piglit/bin/glsl-fs-loop -auto -fbo":
Indirect leak of 120 byte(s) in 5 object(s) allocated from:
    #0 0x7f8e7930ef57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57)
    #1 0x7f8e6dc8c68a in __gnu_cxx::new_allocator<std::_List_node<nir_intrinsic_instr*> >::allocate(unsigned long, void const*) /usr/include/c++/11.4.0/ext/new_allocator.h:127
    #2 0x7f8e6dc8c68a in std::allocator_traits<std::allocator<std::_List_node<nir_intrinsic_instr*> > >::allocate(std::allocator<std::_List_node<nir_intrinsic_instr*> >&, unsigned long) /usr/include/c++/11.4.0/bits/alloc_traits.h:464
    #3 0x7f8e6dc8c68a in std::__cxx11::_List_base<nir_intrinsic_instr*, std::allocator<nir_intrinsic_instr*> >::_M_get_node() /usr/include/c++/11.4.0/bits/stl_list.h:443
    #4 0x7f8e6dc8c68a in std::_List_node<nir_intrinsic_instr*>* std::__cxx11::list<nir_intrinsic_instr*, std::allocator<nir_intrinsic_instr*> >::_M_create_node<nir_intrinsic_instr* const&>(nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:635
    #5 0x7f8e6dc8c68a in void std::__cxx11::list<nir_intrinsic_instr*, std::allocator<nir_intrinsic_instr*> >::_M_insert<nir_intrinsic_instr* const&>(std::_List_iterator<nir_intrinsic_instr*>, nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:1912
    #6 0x7f8e6dc8c68a in std::__cxx11::list<nir_intrinsic_instr*, std::allocator<nir_intrinsic_instr*> >::push_back(nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:1213
    #7 0x7f8e6dc8c68a in r600::Shader::scan_instruction(nir_instr*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:655
    #8 0x7f8e6dc8cc2a in r600::Shader::scan_shader(nir_function const*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:554
    #9 0x7f8e6dcab5bc in r600::Shader::process(nir_shader*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:526
    #10 0x7f8e6dcabae1 in r600::Shader::translate_from_nir(nir_shader*, pipe_stream_output_info const*, r600_shader*, r600_shader_key const&, r600_chip_class, radeon_family) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:494
    #11 0x7f8e6da5bf15 in r600_shader_from_nir ../src/gallium/drivers/r600/r600_sfn.cpp:111
    #12 0x7f8e6da5db2c in r600_pipe_shader_create ../src/gallium/drivers/r600/r600_shader.c:198
    #13 0x7f8e6da95c62 in r600_shader_select ../src/gallium/drivers/r600/r600_state_common.c:961
    #14 0x7f8e6da9c09f in r600_update_derived_state ../src/gallium/drivers/r600/r600_state_common.c:1888
    #15 0x7f8e6da9c09f in r600_draw_vbo ../src/gallium/drivers/r600/r600_state_common.c:2219
    #16 0x7f8e6d55229d in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1782
    #17 0x7f8e6c5d6322 in _mesa_draw_arrays ../src/mesa/main/draw.c:1204

Fixes: 5de814171b ("r600/sfn: Allow skipping backend shader optimization for a subset of shaders")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27334>
 2024-09-30 21:16:56 +00:00
David Heidelberg 51f04dc804 freedreno/ir3: Do not allow 16-bit mad.x24 
Doesn't work with half registers. For 16-bit operations, there is mad.x16.

Cc: mesa-stable
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31334>
 2024-09-30 20:14:06 +00:00
David Heidelberg c36cc1fdf2 freedreno/ir3: mad.x24 is not safe to lower 
Fixes following piglit tests on Adreno 630:
program@execute@builtin@builtin-char-mad_sat-1.0.generated
program@execute@builtin@builtin-uchar-mad_sat-1.0.generated

Cc: mesa-stable
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31334>
 2024-09-30 20:14:06 +00:00
Eric R. Smith 5fdc82d5f1 panfrost: fix earlyzs settings for alpha_to_coverage 
When alpha_to_coverage is enabled, the zs_update_operation field
must be set to force_late, according to (some of) the documentation.
Actually the docs are ambiguous; the main thrust is that late coverage
updates are only required when Z or S is written, or when occlusion
queries are enabled. But there is a side note in a table that indicates
force_late should be used for coverage updates even if Z or S is not
written.

Logically this shouldn't be necessary and the note is probably
just lazily written. But it turns out that we do seem to need the
force_late setting on valhall. It's currently unclear whether
there's a hardware issue on valhall, or some other issue.

Fixes piglit ext_framebuffer_multisample-*alpha-to-coverage* tests
on valhall.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31181>
 2024-09-30 18:33:41 +00:00
Mike Blumenkrantz 83495533b0 zink: revert compression control handling 
I misunderstood how this works, and there is no general format-query,
which may mean the current gallium interface is unimplementable

This reverts commit 735e402ae4.
This reverts commit 9696df4132.
This reverts commit 33c1b940e0.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31444>
 2024-09-30 17:57:11 +00:00
Erik Faye-Lund 4ae273dcf4 mesa: make compressed-format emulation optional 
There's good reasons to emulate compressed formats; mobile and desktop
HW generally have different ideas of what formats are worth the extra
silicon, so they support different formats based on the legacy they were
designed to support. This means we can get better application
compatibility by emulating these formats.

But, that comes at a price, namely that applications that supports
multiple formats don't really have a way to detect which ones are
natively supported and which ones are not. This means they might make
the wrong choice, and end up wasting memory and bandwidth when that
could have been avoided.

So let's make the emulation optional, by introducing a DRIconf variable
to disable it.

This intentionally still leaves in place transcoding support, because
that's still *probably* a win. Besides, those needs to be opted into
anyway.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31420>
 2024-09-30 17:18:19 +00:00
Vitaliy Triang3l Kuzmin 0a70207648 r600: Add missing formats to r600_colorformat_endian_swap 
Adds all formats that can be returned by r600_translate_colorformat.

Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23005>
 2024-09-30 14:11:56 +00:00
Corentin Noël bef454f227 virgl: Avoid a race condition on handle removal 
We were unlocking the bo handles hash table right after removing the bo handle
and afterward closing it. This leads to race conditions where the handle could
have been re-acquired on another thread. As the kernel would return the same
bo handle and do not reference count them, this leads to it being used after
being closed.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31421>
 2024-09-30 13:23:10 +00:00
Vitaliy Triang3l Kuzmin 659d88e7fc r600: Add FMT_1_REVERSED to r600_formats.h 
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23010>
 2024-09-30 12:48:08 +00:00
Juan A. Suarez Romero 9b3399b3f7 vc4: handle nir_op_ult32 intrinsic 
Fixes `spec@glsl-1.10@execution@vs-loop-partial-unroll-multiple-breaks`.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31427>
 2024-09-30 12:16:54 +00:00
Mauro Rossi 15bea329d7 android: gbm: split the DRI backend into separate library 
Changes required after commit 514df444e

dri_gbm module is installed as /vendor/lib{64}/dri_gbm.so
to avoid changes in system/linkerconfig AOSP project

gbm-backends-path option is set as /vendor/$(MESA3D_LIB_DIR)

MESA3D_GBM_BINS variable simplifies dependencies declarations

Test results: gbm_gralloc works again

Fixes: 514df444e ("gbm: split the DRI backend into a separate library and unify backend handling")
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31428>
 2024-09-30 13:56:19 +02:00
Tomson Chang fdbdda8c9a amd/vpelib: Only update cached adjustment when it is valid 
Only update cached adjustment when it is valid.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31274>
 2024-09-30 10:12:14 +00:00
Tomson Chang 52289f4ab2 amd/vpelib: Fix color adjustment change detect hole 
When color adjustment changed from custom values to default values, the
useColorAdj will be false and the code to update new stream ctx color adj
will be skipped, thus when the color adj changes to the same custom values
later, it will show as "not dirty", causing custom color adj not taking effect
unless its value changed.

We should always update the new steam ctx color adj no matter it is default or not.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31274>
 2024-09-30 10:12:14 +00:00
Jude Shih dba0c98ca5 amd/vpelib: Dynamic Command List Expansion 
1. Implement a vector like data structure to expand
command list memory dynamically.
2. The size will be doubled once we reach its capacity.
3. Make vector a generic util under utils folder.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Reviewed-by: Jesse Agate <jesse.agate@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31274>
 2024-09-30 10:12:14 +00:00
Roy Chan b2ce281319 amd/vpelib: fix zero input handling 
[why]
Fix in 0 input stream, it would crash in accessing null param->streams.

[how]
- Only use stream_ctx->stream instead of param->stream in color
  handling.
- Revise the geometric downscaling support.

Reviewed-by: Tomson Chang <tomson.chang@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Roy Chan <roy.chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31274>
 2024-09-30 10:12:14 +00:00
Roy Chan acde345606 amd/vpelib: Optimize the CPU usage by caching all the LUT configs 
[why]
The fix point conversion takes quite a bit of CPU time.
And if there are no changes, we don't need to convert all sw points
into hw points and generate the corresponding configs.

[how]
Introduce a config cache header so that all config caching handlings
can be done in the same way.

Luts won't be cached if it is in bypass mode, only cache when it is
non bypass and some dirty flag is set by the upper layer.
The config cache handling will re-apply the cached config if not
dirty and not in bypass mode.

Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Roy Chan <roy.chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31274>
 2024-09-30 10:12:14 +00:00
Jesse ee590ee91a amd/vpelib: Config Writer hook and CDC refinement 
Generalize CDC and config writer hook.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Jesse Agate <jesse.agate@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31274>
 2024-09-30 10:12:14 +00:00
Rhys Perry 7f092cbd91 aco: workaround hazards in emit_long_jump 
fossil-db (navi31):
Totals from 29 (0.04% of 79395) affected shaders:
CodeSize: 17612888 -> 17615096 (+0.01%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31316>
 2024-09-30 09:04:35 +00:00
Rhys Perry 9fb97085d1 aco/tests: update assembler tests for llvm 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31316>
 2024-09-30 09:04:35 +00:00
Kenneth Graunke 0b34a7aff0 nir: Don't generate single iteration loops to zero-initialize memory 
If the stride we're adding to our loop counter is larger than the total
amount of shared local memory we're trying to initialize, we know the
loop will run at most one time.  So we can skip emitting a loop.

Loop unrolling appears to be unable to detect this currently.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31312>
 2024-09-30 05:27:17 +00:00
Tapani Pälli c1a44e8d43 anv: force StackIDControl value for Wa_14021821874 
This is also encouraged by another wa, Wa_14018813551.

Both workarounds state that StackIDControlOverride_RTGlobals should
always be set to 0 (i.e. 2k).

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30937>
 2024-09-30 07:33:37 +03:00
Mike Blumenkrantz 9b51cb05d2 ci: bump VVL to current week 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31432>
 2024-09-29 22:26:46 +00:00
Pavel Ondračka cd40732b25 r300: get rid of unneeded CMP before KIL 
NIR discard_if expects bools, therefore we end with extr CMP in
the end, however we can handle floats just fine (only with the
reversed logic, so it triggers for src < 0).

Shader-db RV530:
total instructions in shared programs: 120787 -> 120687 (-0.08%)
instructions in affected programs: 5559 -> 5459 (-1.80%)
helped: 102
HURT: 8
total temps in shared programs: 16770 -> 16764 (-0.04%)
temps in affected programs: 151 -> 145 (-3.97%)
helped: 8
HURT: 5
total cycles in shared programs: 181520 -> 181444 (-0.04%)
cycles in affected programs: 10932 -> 10856 (-0.70%)
helped: 101
HURT: 12

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30967>
 2024-09-29 14:13:50 +00:00