r600/sfn: fix class Shader object m_register_allocations memory leak

For instance, this issue is triggered with "piglit/bin/glsl-fs-loop -auto -fbo":
Indirect leak of 120 byte(s) in 5 object(s) allocated from:
    #0 0x7f8e7930ef57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57)
    #1 0x7f8e6dc8c68a in __gnu_cxx::new_allocator<std::_List_node<nir_intrinsic_instr*> >::allocate(unsigned long, void const*) /usr/include/c++/11.4.0/ext/new_allocator.h:127
    #2 0x7f8e6dc8c68a in std::allocator_traits<std::allocator<std::_List_node<nir_intrinsic_instr*> > >::allocate(std::allocator<std::_List_node<nir_intrinsic_instr*> >&, unsigned long) /usr/include/c++/11.4.0/bits/alloc_traits.h:464
    #3 0x7f8e6dc8c68a in std::__cxx11::_List_base<nir_intrinsic_instr*, std::allocator<nir_intrinsic_instr*> >::_M_get_node() /usr/include/c++/11.4.0/bits/stl_list.h:443
    #4 0x7f8e6dc8c68a in std::_List_node<nir_intrinsic_instr*>* std::__cxx11::list<nir_intrinsic_instr*, std::allocator<nir_intrinsic_instr*> >::_M_create_node<nir_intrinsic_instr* const&>(nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:635
    #5 0x7f8e6dc8c68a in void std::__cxx11::list<nir_intrinsic_instr*, std::allocator<nir_intrinsic_instr*> >::_M_insert<nir_intrinsic_instr* const&>(std::_List_iterator<nir_intrinsic_instr*>, nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:1912
    #6 0x7f8e6dc8c68a in std::__cxx11::list<nir_intrinsic_instr*, std::allocator<nir_intrinsic_instr*> >::push_back(nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:1213
    #7 0x7f8e6dc8c68a in r600::Shader::scan_instruction(nir_instr*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:655
    #8 0x7f8e6dc8cc2a in r600::Shader::scan_shader(nir_function const*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:554
    #9 0x7f8e6dcab5bc in r600::Shader::process(nir_shader*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:526
    #10 0x7f8e6dcabae1 in r600::Shader::translate_from_nir(nir_shader*, pipe_stream_output_info const*, r600_shader*, r600_shader_key const&, r600_chip_class, radeon_family) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:494
    #11 0x7f8e6da5bf15 in r600_shader_from_nir ../src/gallium/drivers/r600/r600_sfn.cpp:111
    #12 0x7f8e6da5db2c in r600_pipe_shader_create ../src/gallium/drivers/r600/r600_shader.c:198
    #13 0x7f8e6da95c62 in r600_shader_select ../src/gallium/drivers/r600/r600_state_common.c:961
    #14 0x7f8e6da9c09f in r600_update_derived_state ../src/gallium/drivers/r600/r600_state_common.c:1888
    #15 0x7f8e6da9c09f in r600_draw_vbo ../src/gallium/drivers/r600/r600_state_common.c:2219
    #16 0x7f8e6d55229d in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1782
    #17 0x7f8e6c5d6322 in _mesa_draw_arrays ../src/mesa/main/draw.c:1204

Fixes: 5de814171b ("r600/sfn: Allow skipping backend shader optimization for a subset of shaders")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27334>

src/gallium/drivers/r600/sfn/sfn_shader.h

@@ -403,7 +403,7 @@ private:
    InstructionChain m_chain_instr;
    std::list<Instr *, Allocator<Instr *>> m_loops;
    int m_control_flow_depth{0};
-   std::list<nir_intrinsic_instr*> m_register_allocations;
+   ValueFactory::nir_intrinsic_instr_alloc m_register_allocations;
 };
 
 } // namespace r600

src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp

@@ -33,7 +33,7 @@ ValueFactory::set_virtual_register_base(int base)
 }
 
 bool
-ValueFactory::allocate_registers(const std::list<nir_intrinsic_instr *>& regs)
+ValueFactory::allocate_registers(const nir_intrinsic_instr_alloc& regs)
 {
    struct array_entry {
       unsigned index;

src/gallium/drivers/r600/sfn/sfn_valuefactory.h

@@ -204,9 +204,11 @@ public:
 
    int new_register_index();
 
+   using nir_intrinsic_instr_alloc =
+      std::list<nir_intrinsic_instr *, Allocator<nir_intrinsic_instr *>>;
 
    /* Allocate registers */
-   bool allocate_registers(const std::list<nir_intrinsic_instr *>& regs);
+   bool allocate_registers(const nir_intrinsic_instr_alloc& regs);
    PRegister allocate_pinned_register(int sel, int chan);
    RegisterVec4 allocate_pinned_vec4(int sel, bool is_ssa);