From b660c7369318079ad61628f0540fceb0e08e8b6d Mon Sep 17 00:00:00 2001 From: Patrick Lerda Date: Mon, 22 Jan 2024 15:29:35 +0100 Subject: [PATCH] r600/sfn: fix class Shader object m_register_allocations memory leak For instance, this issue is triggered with "piglit/bin/glsl-fs-loop -auto -fbo": Indirect leak of 120 byte(s) in 5 object(s) allocated from: #0 0x7f8e7930ef57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57) #1 0x7f8e6dc8c68a in __gnu_cxx::new_allocator >::allocate(unsigned long, void const*) /usr/include/c++/11.4.0/ext/new_allocator.h:127 #2 0x7f8e6dc8c68a in std::allocator_traits > >::allocate(std::allocator >&, unsigned long) /usr/include/c++/11.4.0/bits/alloc_traits.h:464 #3 0x7f8e6dc8c68a in std::__cxx11::_List_base >::_M_get_node() /usr/include/c++/11.4.0/bits/stl_list.h:443 #4 0x7f8e6dc8c68a in std::_List_node* std::__cxx11::list >::_M_create_node(nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:635 #5 0x7f8e6dc8c68a in void std::__cxx11::list >::_M_insert(std::_List_iterator, nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:1912 #6 0x7f8e6dc8c68a in std::__cxx11::list >::push_back(nir_intrinsic_instr* const&) /usr/include/c++/11.4.0/bits/stl_list.h:1213 #7 0x7f8e6dc8c68a in r600::Shader::scan_instruction(nir_instr*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:655 #8 0x7f8e6dc8cc2a in r600::Shader::scan_shader(nir_function const*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:554 #9 0x7f8e6dcab5bc in r600::Shader::process(nir_shader*) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:526 #10 0x7f8e6dcabae1 in r600::Shader::translate_from_nir(nir_shader*, pipe_stream_output_info const*, r600_shader*, r600_shader_key const&, r600_chip_class, radeon_family) ../src/gallium/drivers/r600/sfn/sfn_shader.cpp:494 #11 0x7f8e6da5bf15 in r600_shader_from_nir ../src/gallium/drivers/r600/r600_sfn.cpp:111 #12 0x7f8e6da5db2c in r600_pipe_shader_create ../src/gallium/drivers/r600/r600_shader.c:198 #13 0x7f8e6da95c62 in r600_shader_select ../src/gallium/drivers/r600/r600_state_common.c:961 #14 0x7f8e6da9c09f in r600_update_derived_state ../src/gallium/drivers/r600/r600_state_common.c:1888 #15 0x7f8e6da9c09f in r600_draw_vbo ../src/gallium/drivers/r600/r600_state_common.c:2219 #16 0x7f8e6d55229d in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1782 #17 0x7f8e6c5d6322 in _mesa_draw_arrays ../src/mesa/main/draw.c:1204 Fixes: 5de814171bd0 ("r600/sfn: Allow skipping backend shader optimization for a subset of shaders") Signed-off-by: Patrick Lerda Reviewed-by: Gert Wollny Part-of: --- src/gallium/drivers/r600/sfn/sfn_shader.h | 2 +- src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp | 2 +- src/gallium/drivers/r600/sfn/sfn_valuefactory.h | 4 +++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/r600/sfn/sfn_shader.h b/src/gallium/drivers/r600/sfn/sfn_shader.h index 131fe50623e..2b53cf61cfa 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader.h @@ -403,7 +403,7 @@ private: InstructionChain m_chain_instr; std::list> m_loops; int m_control_flow_depth{0}; - std::list m_register_allocations; + ValueFactory::nir_intrinsic_instr_alloc m_register_allocations; }; } // namespace r600 diff --git a/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp b/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp index 1c055b828a9..61749190859 100644 --- a/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp @@ -33,7 +33,7 @@ ValueFactory::set_virtual_register_base(int base) } bool -ValueFactory::allocate_registers(const std::list& regs) +ValueFactory::allocate_registers(const nir_intrinsic_instr_alloc& regs) { struct array_entry { unsigned index; diff --git a/src/gallium/drivers/r600/sfn/sfn_valuefactory.h b/src/gallium/drivers/r600/sfn/sfn_valuefactory.h index 19f87ff705c..a8a70600e13 100644 --- a/src/gallium/drivers/r600/sfn/sfn_valuefactory.h +++ b/src/gallium/drivers/r600/sfn/sfn_valuefactory.h @@ -204,9 +204,11 @@ public: int new_register_index(); + using nir_intrinsic_instr_alloc = + std::list>; /* Allocate registers */ - bool allocate_registers(const std::list& regs); + bool allocate_registers(const nir_intrinsic_instr_alloc& regs); PRegister allocate_pinned_register(int sel, int chan); RegisterVec4 allocate_pinned_vec4(int sel, bool is_ssa);