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aco: fix compact_relocate_vars fallback with scc/exec/m0 precolored regs

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This probably doesn't fix anything in practice. I don't think this path is
ever taken for SGPRs except for pseudo-scalar transcendental instructions,
and those don't have any precolored operands/definitions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34343>
This commit is contained in:
Rhys Perry
2025-03-25 14:41:47 +00:00
committed by Marge Bot
parent f6581b41c4
commit a780345e01
1 changed files with 14 additions and 4 deletions
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src/amd/compiler/aco_register_allocation.cpp
+14 -4
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@@ -1886,20 +1886,28 @@ get_reg(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp,
if (!increase_register_file(ctx, info.rc)) {
/* fallback algorithm: reallocate all variables at once (linear VGPRs should already be
* compact at the end) */
const PhysRegInterval regs = get_reg_bounds(ctx, info.rc);
unsigned def_size = info.rc.size();
for (Definition def : instr->definitions) {
if (def.isPrecolored()) {
assert(!regs.contains({def.physReg(), def.size()}));
continue;
}
if (ctx.assignments[def.tempId()].assigned && def.regClass().type() == info.rc.type())
def_size += def.regClass().size();
}
unsigned killed_op_size = 0;
for (Operand op : instr->operands) {
if (op.isPrecolored()) {
assert(!regs.contains({op.physReg(), op.size()}));
continue;
}
if (op.isTemp() && op.isFirstKillBeforeDef() && op.regClass().type() == info.rc.type())
killed_op_size += op.regClass().size();
}
const PhysRegInterval regs = get_reg_bounds(ctx, info.rc);
/* reallocate passthrough variables and non-killed operands */
std::vector<IDAndRegClass> vars;
for (unsigned id : find_vars(ctx, reg_file, regs))
@@ -1911,7 +1919,8 @@ get_reg(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp,
/* reallocate killed operands */
std::vector<IDAndRegClass> killed_op_vars;
for (Operand op : instr->operands) {
if (op.isFirstKillBeforeDef() && op.regClass().type() == info.rc.type())
if (!op.isPrecolored() && op.isFirstKillBeforeDef() &&
op.regClass().type() == info.rc.type())
killed_op_vars.emplace_back(op.tempId(), op.regClass());
}
compact_relocate_vars(ctx, killed_op_vars, parallelcopies, space);
@@ -1919,7 +1928,8 @@ get_reg(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp,
/* reallocate definitions */
std::vector<IDAndRegClass> def_vars;
for (Definition def : instr->definitions) {
if (ctx.assignments[def.tempId()].assigned && def.regClass().type() == info.rc.type())
if (!def.isPrecolored() && ctx.assignments[def.tempId()].assigned &&
def.regClass().type() == info.rc.type())
def_vars.emplace_back(def.tempId(), def.regClass());
}
def_vars.emplace_back(0xffffffff, info.rc);